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0063dd1708
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented as well, it is possible to control whether PMU counters take into account events happening on other threads. If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit leaving it to effective state of 0 regardless of any write to it. This patch introduces the DISABLE_MTPMU flag, which allows to diable multithread event count from EL3 (or EL2). The flag is disabled by default so the behavior is consistent with those architectures that do not implement FEAT_MTPMU. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
106 lines
2.1 KiB
ArmAsm
106 lines
2.1 KiB
ArmAsm
/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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.global mtpmu_disable
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/* -------------------------------------------------------------
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* The functions in this file are called at entrypoint, before
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* the CPU has decided whether this is a cold or a warm boot.
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* Therefore there are no stack yet to rely on for a C function
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* call.
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* -------------------------------------------------------------
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*/
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/*
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* bool mtpmu_supported(void)
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*
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* Return a boolean indicating whether FEAT_MTPMU is supported or not.
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*
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* Trash registers: r0.
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*/
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func mtpmu_supported
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ldcopr r0, ID_DFR1
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and r0, r0, #(ID_DFR1_MTPMU_MASK >> ID_DFR1_MTPMU_SHIFT)
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cmp r0, #ID_DFR1_MTPMU_SUPPORTED
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mov r0, #0
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addeq r0, r0, #1
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bx lr
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endfunc mtpmu_supported
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/*
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* bool el_implemented(unsigned int el)
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*
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* Return a boolean indicating if the specified EL (2 or 3) is implemented.
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*
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* Trash registers: r0
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*/
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func el_implemented
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cmp r0, #3
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ldcopr r0, ID_PFR1
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lsreq r0, r0, #ID_PFR1_SEC_SHIFT
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lsrne r0, r0, #ID_PFR1_VIRTEXT_SHIFT
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/*
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* ID_PFR1_VIRTEXT_MASK is the same as ID_PFR1_SEC_MASK
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* so use any one of them
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*/
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and r0, r0, #ID_PFR1_VIRTEXT_MASK
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cmp r0, #ID_PFR1_ELx_ENABLED
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mov r0, #0
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addeq r0, r0, #1
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bx lr
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endfunc el_implemented
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/*
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* void mtpmu_disable(void)
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*
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* Disable mtpmu feature if supported.
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*
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* Trash register: r0, r1, r2
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*/
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func mtpmu_disable
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mov r2, lr
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bl mtpmu_supported
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cmp r0, #0
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bxeq r2 /* FEAT_MTPMU not supported */
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/* FEAT_MTMPU Supported */
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mov r0, #3
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bl el_implemented
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cmp r0, #0
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beq 1f
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/* EL3 implemented */
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ldcopr r0, SDCR
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ldr r1, =SDCR_MTPME_BIT
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bic r0, r0, r1
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stcopr r0, SDCR
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/*
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* If EL3 is implemented, HDCR.MTPME is implemented as Res0 and
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* FEAT_MTPMU is controlled only from EL3, so no need to perform
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* any operations for EL2.
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*/
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isb
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bx r2
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1:
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/* EL3 not implemented */
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mov r0, #2
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bl el_implemented
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cmp r0, #0
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bxeq r2 /* No EL2 or EL3 implemented */
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/* EL2 implemented */
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ldcopr r0, HDCR
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ldr r1, =HDCR_MTPME_BIT
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orr r0, r0, r1
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stcopr r0, HDCR
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isb
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bx r2
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endfunc mtpmu_disable
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