Sandrine Bailleux 85d80e5578 Initialize VTTBR_EL2 when bypassing EL2 ... In the situation that EL1 is selected as the exception level for the next image upon BL31 exit for a processor that supports EL2, the context management code must configure all essential EL2 register state to ensure correct execution of EL1. VTTBR_EL2 should be part of this set of EL2 registers because: - The ARMv8-A architecture does not define a reset value for this register. - Cache maintenance operations depend on VTTBR_EL2.VMID even when non-secure EL1&0 stage 2 address translation are disabled. This patch initializes the VTTBR_EL2 register to 0 when bypassing EL2 to address this issue. Note that this bug has not yet manifested itself on FVP or Juno because VTTBR_EL2.VMID resets to 0 on the Cortex-A53 and Cortex-A57. Change-Id: I58ce2d16a71687126f437577a506d93cb5eecf33		2015-12-09 11:34:10 +00:00
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aarch64	Merge pull request #443 from achingupta/sb/el3_payloads-cb_single_cpu	2015-12-01 19:02:24 +00:00
bl31_main.c	Introduce print_entry_point_info() function	2015-11-02 09:23:05 +00:00
bl31.ld.S	Fix relocation of __PERCPU_BAKERY_LOCK_SIZE__	2015-09-25 16:35:10 +01:00
bl31.mk	Remove the IMF_READ_INTERRUPT_ID build option	2015-11-26 17:07:32 +00:00
context_mgmt.c	Initialize VTTBR_EL2 when bypassing EL2	2015-12-09 11:34:10 +00:00
cpu_data_array.c	Rework the crash reporting in BL3-1 to use less stack	2014-07-28 11:03:20 +01:00
interrupt_mgmt.c	IMF: postpone SCR_EL3 update if context is not initialized	2015-11-05 16:36:55 +00:00
runtime_svc.c	Enable type-checking of arguments passed to printf() et al.	2015-03-06 13:07:43 +00:00