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https://github.com/CTCaer/switch-l4t-atf.git
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883d1b5d4a
When the MMU is enabled and the translation tables are mapped, data read/writes to the translation tables are made using the attributes specified in the translation tables themselves. However, the MMU performs table walks with the attributes specified in TCR_ELx. They are completely independent, so special care has to be taken to make sure that they are the same. This has to be done manually because it is not practical to have a test in the code. Such a test would need to know the virtual memory region that contains the translation tables and check that for all of the tables the attributes match the ones in TCR_ELx. As the tables may not even be mapped at all, this isn't a test that can be made generic. The flags used by enable_mmu_xxx() have been moved to the same header where the functions are. Also, some comments in the linker scripts related to the translation tables have been fixed. Change-Id: I1754768bffdae75f53561b1c4a5baf043b45a304 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
155 lines
4.1 KiB
ArmAsm
155 lines
4.1 KiB
ArmAsm
/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <xlat_tables_defs.h>
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OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
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OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(bl2_entrypoint)
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MEMORY {
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RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
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}
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SECTIONS
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{
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. = BL2_BASE;
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ASSERT(. == ALIGN(PAGE_SIZE),
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"BL2_BASE address is not aligned on a page boundary.")
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#if SEPARATE_CODE_AND_RODATA
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.text . : {
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__TEXT_START__ = .;
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*bl2_entrypoint.o(.text*)
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*(.text*)
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*(.vectors)
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. = NEXT(PAGE_SIZE);
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__TEXT_END__ = .;
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} >RAM
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.rodata . : {
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__RODATA_START__ = .;
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*(.rodata*)
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/* Ensure 8-byte alignment for descriptors and ensure inclusion */
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. = ALIGN(8);
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__PARSER_LIB_DESCS_START__ = .;
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KEEP(*(.img_parser_lib_descs))
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__PARSER_LIB_DESCS_END__ = .;
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. = NEXT(PAGE_SIZE);
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__RODATA_END__ = .;
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} >RAM
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#else
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ro . : {
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__RO_START__ = .;
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*bl2_entrypoint.o(.text*)
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*(.text*)
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*(.rodata*)
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/* Ensure 8-byte alignment for descriptors and ensure inclusion */
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. = ALIGN(8);
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__PARSER_LIB_DESCS_START__ = .;
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KEEP(*(.img_parser_lib_descs))
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__PARSER_LIB_DESCS_END__ = .;
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*(.vectors)
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__RO_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked as
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* read-only, executable. No RW data from the next section must
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* creep in. Ensure the rest of the current memory page is unused.
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*/
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. = NEXT(PAGE_SIZE);
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__RO_END__ = .;
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} >RAM
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#endif
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/*
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* Define a linker symbol to mark start of the RW memory area for this
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* image.
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*/
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__RW_START__ = . ;
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/*
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* .data must be placed at a lower address than the stacks if the stack
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* protector is enabled. Alternatively, the .data.stack_protector_canary
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* section can be placed independently of the main .data section.
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*/
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.data . : {
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__DATA_START__ = .;
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*(.data*)
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__DATA_END__ = .;
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} >RAM
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stacks (NOLOAD) : {
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__STACKS_START__ = .;
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*(tzfw_normal_stacks)
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__STACKS_END__ = .;
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} >RAM
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/*
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* The .bss section gets initialised to 0 at runtime.
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* Its base address should be 16-byte aligned for better performance of the
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* zero-initialization code.
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*/
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.bss : ALIGN(16) {
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__BSS_START__ = .;
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*(SORT_BY_ALIGNMENT(.bss*))
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*(COMMON)
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__BSS_END__ = .;
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} >RAM
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/*
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* The xlat_table section is for full, aligned page tables (4K).
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* Removing them from .bss avoids forcing 4K alignment on
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* the .bss section. The tables are initialized to zero by the translation
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* tables library.
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*/
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xlat_table (NOLOAD) : {
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*(xlat_table)
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} >RAM
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#if USE_COHERENT_MEM
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/*
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* The base address of the coherent memory section must be page-aligned (4K)
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* to guarantee that the coherent data are stored on their own pages and
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* are not mixed with normal data. This is required to set up the correct
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* memory attributes for the coherent data page tables.
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*/
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coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
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__COHERENT_RAM_START__ = .;
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*(tzfw_coherent_mem)
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__COHERENT_RAM_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked
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* as device memory. No other unexpected data must creep in.
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* Ensure the rest of the current memory page is unused.
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*/
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. = NEXT(PAGE_SIZE);
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__COHERENT_RAM_END__ = .;
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} >RAM
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#endif
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/*
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* Define a linker symbol to mark end of the RW memory area for this
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* image.
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*/
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__RW_END__ = .;
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__BL2_END__ = .;
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__BSS_SIZE__ = SIZEOF(.bss);
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#if USE_COHERENT_MEM
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__COHERENT_RAM_UNALIGNED_SIZE__ =
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__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
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#endif
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ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
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}
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