Soby Mathew 8cd16e6b5b Build option to include AArch32 registers in cpu context ... The system registers that are saved and restored in CPU context include AArch32 systems registers like SPSR_ABT, SPSR_UND, SPSR_IRQ, SPSR_FIQ, DACR32_EL2, IFSR32_EL2 and FPEXC32_EL2. Accessing these registers on an AArch64-only (i.e. on hardware that does not implement AArch32, or at least not at EL1 and higher ELs) platform leads to an exception. This patch introduces the build option `CTX_INCLUDE_AARCH32_REGS` to specify whether to include these AArch32 systems registers in the cpu context or not. By default this build option is set to 1 to ensure compatibility. AArch64-only platforms must set it to 0. A runtime check is added in BL1 and BL31 cold boot path to verify this. Fixes ARM-software/tf-issues#386 Change-Id: I720cdbd7ed7f7d8516635a2ec80d025f478b95ee		2016-06-03 10:50:52 +01:00
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bl1	FWU: Add Generic Firmware Update framework support in BL1	2015-12-09 17:41:18 +00:00
bl31	Remove direct usage of __attribute__((foo))	2016-01-14 10:55:17 -08:00
bl32	Enable use of FIQs and IRQs as TSP interrupts	2015-12-04 12:02:12 +00:00
common	Build option to include AArch32 registers in cpu context	2016-06-03 10:50:52 +01:00
drivers	Implement generic delay timer	2016-05-20 15:29:30 +01:00
lib	Add support for Cortex-A57 erratum 833471 workaround	2016-04-21 12:59:59 +01:00
plat	Add 32 bit version of plat_get_syscnt_freq	2016-05-20 15:29:03 +01:00
stdlib	cdefs.h: Use __deprecated__ instead of deprecated	2016-01-20 15:45:39 -08:00