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ARM Trusted Firmware Interrupt Management Design guide
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======================================================
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.. section-numbering::
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:suffix: .
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.. contents::
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This framework is responsible for managing interrupts routed to EL3. It also
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allows EL3 software to configure the interrupt routing behavior. Its main
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objective is to implement the following two requirements.
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#. It should be possible to route interrupts meant to be handled by secure
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software (Secure interrupts) to EL3, when execution is in non-secure state
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(normal world). The framework should then take care of handing control of
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the interrupt to either software in EL3 or Secure-EL1 depending upon the
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software configuration and the GIC implementation. This requirement ensures
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that secure interrupts are under the control of the secure software with
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respect to their delivery and handling without the possibility of
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intervention from non-secure software.
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#. It should be possible to route interrupts meant to be handled by
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non-secure software (Non-secure interrupts) to the last executed exception
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level in the normal world when the execution is in secure world at
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exception levels lower than EL3. This could be done with or without the
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knowledge of software executing in Secure-EL1/Secure-EL0. The choice of
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approach should be governed by the secure software. This requirement
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ensures that non-secure software is able to execute in tandem with the
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secure software without overriding it.
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Concepts
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--------
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Interrupt types
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~~~~~~~~~~~~~~~
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The framework categorises an interrupt to be one of the following depending upon
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the exception level(s) it is handled in.
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#. Secure EL1 interrupt. This type of interrupt can be routed to EL3 or
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Secure-EL1 depending upon the security state of the current execution
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context. It is always handled in Secure-EL1.
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#. Non-secure interrupt. This type of interrupt can be routed to EL3,
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Secure-EL1, Non-secure EL1 or EL2 depending upon the security state of the
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current execution context. It is always handled in either Non-secure EL1
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or EL2.
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#. EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1
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depending upon the security state of the current execution context. It is
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always handled in EL3.
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The following constants define the various interrupt types in the framework
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implementation.
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::
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#define INTR_TYPE_S_EL1 0
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#define INTR_TYPE_EL3 1
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#define INTR_TYPE_NS 2
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Routing model
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~~~~~~~~~~~~~
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A type of interrupt can be either generated as an FIQ or an IRQ. The target
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exception level of an interrupt type is configured through the FIQ and IRQ bits
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in the Secure Configuration Register at EL3 (``SCR_EL3.FIQ`` and ``SCR_EL3.IRQ``
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bits). When ``SCR_EL3.FIQ``\ =1, FIQs are routed to EL3. Otherwise they are routed
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to the First Exception Level (FEL) capable of handling interrupts. When
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``SCR_EL3.IRQ``\ =1, IRQs are routed to EL3. Otherwise they are routed to the
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FEL. This register is configured independently by EL3 software for each security
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state prior to entry into a lower exception level in that security state.
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A routing model for a type of interrupt (generated as FIQ or IRQ) is defined as
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its target exception level for each security state. It is represented by a
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single bit for each security state. A value of ``0`` means that the interrupt
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should be routed to the FEL. A value of ``1`` means that the interrupt should be
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routed to EL3. A routing model is applicable only when execution is not in EL3.
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The default routing model for an interrupt type is to route it to the FEL in
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either security state.
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Valid routing models
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~~~~~~~~~~~~~~~~~~~~
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The framework considers certain routing models for each type of interrupt to be
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incorrect as they conflict with the requirements mentioned in Section 1. The
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following sub-sections describe all the possible routing models and specify
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which ones are valid or invalid. EL3 interrupts are currently supported only
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for GIC version 3.0 (ARM GICv3) and only the Secure-EL1 and Non-secure interrupt
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types are supported for GIC version 2.0 (ARM GICv2) (See 1.2). The terminology
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used in the following sub-sections is explained below.
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#. **CSS**. Current Security State. ``0`` when secure and ``1`` when non-secure
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#. **TEL3**. Target Exception Level 3. ``0`` when targeted to the FEL. ``1`` when
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targeted to EL3.
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Secure-EL1 interrupts
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^^^^^^^^^^^^^^^^^^^^^
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#. **CSS=0, TEL3=0**. Interrupt is routed to the FEL when execution is in
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secure state. This is a valid routing model as secure software is in
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control of handling secure interrupts.
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#. **CSS=0, TEL3=1**. Interrupt is routed to EL3 when execution is in secure
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state. This is a valid routing model as secure software in EL3 can
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handover the interrupt to Secure-EL1 for handling.
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#. **CSS=1, TEL3=0**. Interrupt is routed to the FEL when execution is in
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non-secure state. This is an invalid routing model as a secure interrupt
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is not visible to the secure software which violates the motivation behind
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the ARM Security Extensions.
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#. **CSS=1, TEL3=1**. Interrupt is routed to EL3 when execution is in
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non-secure state. This is a valid routing model as secure software in EL3
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can handover the interrupt to Secure-EL1 for handling.
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Non-secure interrupts
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^^^^^^^^^^^^^^^^^^^^^
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#. **CSS=0, TEL3=0**. Interrupt is routed to the FEL when execution is in
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secure state. This allows the secure software to trap non-secure
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interrupts, perform its book-keeping and hand the interrupt to the
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non-secure software through EL3. This is a valid routing model as secure
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software is in control of how its execution is preempted by non-secure
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interrupts.
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#. **CSS=0, TEL3=1**. Interrupt is routed to EL3 when execution is in secure
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state. This is a valid routing model as secure software in EL3 can save
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the state of software in Secure-EL1/Secure-EL0 before handing the
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interrupt to non-secure software. This model requires additional
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coordination between Secure-EL1 and EL3 software to ensure that the
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former's state is correctly saved by the latter.
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#. **CSS=1, TEL3=0**. Interrupt is routed to FEL when execution is in
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non-secure state. This is an valid routing model as a non-secure interrupt
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is handled by non-secure software.
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#. **CSS=1, TEL3=1**. Interrupt is routed to EL3 when execution is in
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non-secure state. This is an invalid routing model as there is no valid
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reason to route the interrupt to EL3 software and then hand it back to
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non-secure software for handling.
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EL3 interrupts
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^^^^^^^^^^^^^^
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#. **CSS=0, TEL3=0**. Interrupt is routed to the FEL when execution is in
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Secure-EL1/Secure-EL0. This is a valid routing model as secure software
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in Secure-EL1/Secure-EL0 is in control of how its execution is preempted
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by EL3 interrupt and can handover the interrupt to EL3 for handling.
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#. **CSS=0, TEL3=1**. Interrupt is routed to EL3 when execution is in
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Secure-EL1/Secure-EL0. This is a valid routing model as secure software
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in EL3 can handle the interrupt.
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#. **CSS=1, TEL3=0**. Interrupt is routed to the FEL when execution is in
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non-secure state. This is an invalid routing model as a secure interrupt
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is not visible to the secure software which violates the motivation behind
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the ARM Security Extensions.
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#. **CSS=1, TEL3=1**. Interrupt is routed to EL3 when execution is in
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non-secure state. This is a valid routing model as secure software in EL3
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can handle the interrupt.
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Mapping of interrupt type to signal
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The framework is meant to work with any interrupt controller implemented by a
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platform. A interrupt controller could generate a type of interrupt as either an
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FIQ or IRQ signal to the CPU depending upon the current security state. The
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mapping between the type and signal is known only to the platform. The framework
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uses this information to determine whether the IRQ or the FIQ bit should be
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programmed in ``SCR_EL3`` while applying the routing model for a type of
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interrupt. The platform provides this information through the
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``plat_interrupt_type_to_line()`` API (described in the
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`Porting Guide`_). For example, on the FVP port when the platform uses an ARM GICv2
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interrupt controller, Secure-EL1 interrupts are signaled through the FIQ signal
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while Non-secure interrupts are signaled through the IRQ signal. This applies
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when execution is in either security state.
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Effect of mapping of several interrupt types to one signal
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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It should be noted that if more than one interrupt type maps to a single
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interrupt signal, and if any one of the interrupt type sets **TEL3=1** for a
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particular security state, then interrupt signal will be routed to EL3 when in
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that security state. This means that all the other interrupt types using the
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same interrupt signal will be forced to the same routing model. This should be
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borne in mind when choosing the routing model for an interrupt type.
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For example, in ARM GICv3, when the execution context is Secure-EL1/
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Secure-EL0, both the EL3 and the non secure interrupt types map to the FIQ
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signal. So if either one of the interrupt type sets the routing model so
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that **TEL3=1** when **CSS=0**, the FIQ bit in ``SCR_EL3`` will be programmed to
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route the FIQ signal to EL3 when executing in Secure-EL1/Secure-EL0, thereby
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effectively routing the other interrupt type also to EL3.
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Assumptions in Interrupt Management Framework
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---------------------------------------------
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The framework makes the following assumptions to simplify its implementation.
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#. Although the framework has support for 2 types of secure interrupts (EL3
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and Secure-EL1 interrupt), only interrupt controller architectures
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like ARM GICv3 has architectural support for EL3 interrupts in the form of
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Group 0 interrupts. In ARM GICv2, all secure interrupts are assumed to be
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handled in Secure-EL1. They can be delivered to Secure-EL1 via EL3 but they
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cannot be handled in EL3.
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#. Interrupt exceptions (``PSTATE.I`` and ``F`` bits) are masked during execution
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in EL3.
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#. .. rubric:: Interrupt management
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:name: interrupt-management
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The following sections describe how interrupts are managed by the interrupt
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handling framework. This entails:
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#. Providing an interface to allow registration of a handler and specification
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of the routing model for a type of interrupt.
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#. Implementing support to hand control of an interrupt type to its registered
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handler when the interrupt is generated.
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Both aspects of interrupt management involve various components in the secure
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software stack spanning from EL3 to Secure-EL1. These components are described
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in the section 2.1. The framework stores information associated with each type
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of interrupt in the following data structure.
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.. code:: c
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typedef struct intr_type_desc {
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interrupt_type_handler_t handler;
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uint32_t flags;
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uint32_t scr_el3[2];
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} intr_type_desc_t;
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The ``flags`` field stores the routing model for the interrupt type in
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bits[1:0]. Bit[0] stores the routing model when execution is in the secure
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state. Bit[1] stores the routing model when execution is in the non-secure
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state. As mentioned in Section 1.2.2, a value of ``0`` implies that the interrupt
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should be targeted to the FEL. A value of ``1`` implies that it should be targeted
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to EL3. The remaining bits are reserved and SBZ. The helper macro
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``set_interrupt_rm_flag()`` should be used to set the bits in the ``flags``
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parameter.
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The ``scr_el3[2]`` field also stores the routing model but as a mapping of the
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model in the ``flags`` field to the corresponding bit in the ``SCR_EL3`` for each
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security state.
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The framework also depends upon the platform port to configure the interrupt
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controller to distinguish between secure and non-secure interrupts. The platform
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is expected to be aware of the secure devices present in the system and their
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associated interrupt numbers. It should configure the interrupt controller to
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enable the secure interrupts, ensure that their priority is always higher than
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the non-secure interrupts and target them to the primary CPU. It should also
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export the interface described in the `Porting Guide`_ to enable
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handling of interrupts.
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In the remainder of this document, for the sake of simplicity a ARM GICv2 system
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is considered and it is assumed that the FIQ signal is used to generate Secure-EL1
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interrupts and the IRQ signal is used to generate non-secure interrupts in either
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security state. EL3 interrupts are not considered.
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Software components
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-------------------
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Roles and responsibilities for interrupt management are sub-divided between the
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following components of software running in EL3 and Secure-EL1. Each component is
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briefly described below.
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#. EL3 Runtime Firmware. This component is common to all ports of the ARM
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Trusted Firmware.
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#. Secure Payload Dispatcher (SPD) service. This service interfaces with the
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Secure Payload (SP) software which runs in Secure-EL1/Secure-EL0 and is
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responsible for switching execution between secure and non-secure states.
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A switch is triggered by a Secure Monitor Call and it uses the APIs
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exported by the Context management library to implement this functionality.
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Switching execution between the two security states is a requirement for
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interrupt management as well. This results in a significant dependency on
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the SPD service. ARM Trusted firmware implements an example Test Secure
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Payload Dispatcher (TSPD) service.
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An SPD service plugs into the EL3 runtime firmware and could be common to
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some ports of the ARM Trusted Firmware.
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#. Secure Payload (SP). On a production system, the Secure Payload corresponds
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to a Secure OS which runs in Secure-EL1/Secure-EL0. It interfaces with the
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SPD service to manage communication with non-secure software. ARM Trusted
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Firmware implements an example secure payload called Test Secure Payload
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(TSP) which runs only in Secure-EL1.
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A Secure payload implementation could be common to some ports of the ARM
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Trusted Firmware just like the SPD service.
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Interrupt registration
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----------------------
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This section describes in detail the role of each software component (see 2.1)
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during the registration of a handler for an interrupt type.
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EL3 runtime firmware
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~~~~~~~~~~~~~~~~~~~~
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This component declares the following prototype for a handler of an interrupt type.
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.. code:: c
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typedef uint64_t (*interrupt_type_handler_t)(uint32_t id,
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uint32_t flags,
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void *handle,
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void *cookie);
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The ``id`` is parameter is reserved and could be used in the future for passing
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the interrupt id of the highest pending interrupt only if there is a foolproof
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way of determining the id. Currently it contains ``INTR_ID_UNAVAILABLE``.
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The ``flags`` parameter contains miscellaneous information as follows.
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#. Security state, bit[0]. This bit indicates the security state of the lower
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exception level when the interrupt was generated. A value of ``1`` means
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that it was in the non-secure state. A value of ``0`` indicates that it was
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in the secure state. This bit can be used by the handler to ensure that
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interrupt was generated and routed as per the routing model specified
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during registration.
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#. Reserved, bits[31:1]. The remaining bits are reserved for future use.
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The ``handle`` parameter points to the ``cpu_context`` structure of the current CPU
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for the security state specified in the ``flags`` parameter.
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Once the handler routine completes, execution will return to either the secure
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or non-secure state. The handler routine must return a pointer to
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``cpu_context`` structure of the current CPU for the target security state. On
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AArch64, this return value is currently ignored by the caller as the
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appropriate ``cpu_context`` to be used is expected to be set by the handler
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via the context management library APIs.
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A portable interrupt handler implementation must set the target context both in
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the structure pointed to by the returned pointer and via the context management
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library APIs. The handler should treat all error conditions as critical errors
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and take appropriate action within its implementation e.g. use assertion
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failures.
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The runtime firmware provides the following API for registering a handler for a
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particular type of interrupt. A Secure Payload Dispatcher service should use
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this API to register a handler for Secure-EL1 and optionally for non-secure
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interrupts. This API also requires the caller to specify the routing model for
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the type of interrupt.
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.. code:: c
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int32_t register_interrupt_type_handler(uint32_t type,
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interrupt_type_handler handler,
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uint64_t flags);
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The ``type`` parameter can be one of the three interrupt types listed above i.e.
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``INTR_TYPE_S_EL1``, ``INTR_TYPE_NS`` & ``INTR_TYPE_EL3``. The ``flags`` parameter
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is as described in Section 2.
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The function will return ``0`` upon a successful registration. It will return
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``-EALREADY`` in case a handler for the interrupt type has already been
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registered. If the ``type`` is unrecognised or the ``flags`` or the ``handler`` are
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invalid it will return ``-EINVAL``.
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Interrupt routing is governed by the configuration of the ``SCR_EL3.FIQ/IRQ`` bits
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prior to entry into a lower exception level in either security state. The
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context management library maintains a copy of the ``SCR_EL3`` system register for
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each security state in the ``cpu_context`` structure of each CPU. It exports the
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following APIs to let EL3 Runtime Firmware program and retrieve the routing
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model for each security state for the current CPU. The value of ``SCR_EL3`` stored
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in the ``cpu_context`` is used by the ``el3_exit()`` function to program the
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``SCR_EL3`` register prior to returning from the EL3 exception level.
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.. code:: c
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uint32_t cm_get_scr_el3(uint32_t security_state);
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void cm_write_scr_el3_bit(uint32_t security_state,
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uint32_t bit_pos,
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uint32_t value);
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``cm_get_scr_el3()`` returns the value of the ``SCR_EL3`` register for the specified
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security state of the current CPU. ``cm_write_scr_el3()`` writes a ``0`` or ``1`` to
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the bit specified by ``bit_pos``. ``register_interrupt_type_handler()`` invokes
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``set_routing_model()`` API which programs the ``SCR_EL3`` according to the routing
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model using the ``cm_get_scr_el3()`` and ``cm_write_scr_el3_bit()`` APIs.
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It is worth noting that in the current implementation of the framework, the EL3
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runtime firmware is responsible for programming the routing model. The SPD is
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responsible for ensuring that the routing model has been adhered to upon
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receiving an interrupt.
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Secure payload dispatcher
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~~~~~~~~~~~~~~~~~~~~~~~~~
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A SPD service is responsible for determining and maintaining the interrupt
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routing model supported by itself and the Secure Payload. It is also responsible
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for ferrying interrupts between secure and non-secure software depending upon
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the routing model. It could determine the routing model at build time or at
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runtime. It must use this information to register a handler for each interrupt
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type using the ``register_interrupt_type_handler()`` API in EL3 runtime firmware.
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If the routing model is not known to the SPD service at build time, then it must
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be provided by the SP as the result of its initialisation. The SPD should
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program the routing model only after SP initialisation has completed e.g. in the
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SPD initialisation function pointed to by the ``bl32_init`` variable.
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The SPD should determine the mechanism to pass control to the Secure Payload
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after receiving an interrupt from the EL3 runtime firmware. This information
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could either be provided to the SPD service at build time or by the SP at
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runtime.
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Test secure payload dispatcher behavior
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The TSPD only handles Secure-EL1 interrupts and is provided with the following
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routing model at build time.
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- Secure-EL1 interrupts are routed to EL3 when execution is in non-secure
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state and are routed to the FEL when execution is in the secure state
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i.e **CSS=0, TEL3=0** & **CSS=1, TEL3=1** for Secure-EL1 interrupts
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- When the build flag ``TSP_NS_INTR_ASYNC_PREEMPT`` is zero, the default routing
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model is used for non-secure interrupts. They are routed to the FEL in
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either security state i.e **CSS=0, TEL3=0** & **CSS=1, TEL3=0** for
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Non-secure interrupts.
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- When the build flag ``TSP_NS_INTR_ASYNC_PREEMPT`` is defined to 1, then the
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non secure interrupts are routed to EL3 when execution is in secure state
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i.e **CSS=0, TEL3=1** for non-secure interrupts. This effectively preempts
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Secure-EL1. The default routing model is used for non secure interrupts in
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non-secure state. i.e **CSS=1, TEL3=0**.
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It performs the following actions in the ``tspd_init()`` function to fulfill the
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requirements mentioned earlier.
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#. It passes control to the Test Secure Payload to perform its
|
|
initialisation. The TSP provides the address of the vector table
|
|
``tsp_vectors`` in the SP which also includes the handler for Secure-EL1
|
|
interrupts in the ``sel1_intr_entry`` field. The TSPD passes control to the TSP at
|
|
this address when it receives a Secure-EL1 interrupt.
|
|
|
|
The handover agreement between the TSP and the TSPD requires that the TSPD
|
|
masks all interrupts (``PSTATE.DAIF`` bits) when it calls
|
|
``tsp_sel1_intr_entry()``. The TSP has to preserve the callee saved general
|
|
purpose, SP\_EL1/Secure-EL0, LR, VFP and system registers. It can use
|
|
``x0-x18`` to enable its C runtime.
|
|
|
|
#. The TSPD implements a handler function for Secure-EL1 interrupts. This
|
|
function is registered with the EL3 runtime firmware using the
|
|
``register_interrupt_type_handler()`` API as follows
|
|
|
|
.. code:: c
|
|
|
|
/* Forward declaration */
|
|
interrupt_type_handler tspd_secure_el1_interrupt_handler;
|
|
int32_t rc, flags = 0;
|
|
set_interrupt_rm_flag(flags, NON_SECURE);
|
|
rc = register_interrupt_type_handler(INTR_TYPE_S_EL1,
|
|
tspd_secure_el1_interrupt_handler,
|
|
flags);
|
|
if (rc)
|
|
panic();
|
|
|
|
#. When the build flag ``TSP_NS_INTR_ASYNC_PREEMPT`` is defined to 1, the TSPD
|
|
implements a handler function for non-secure interrupts. This function is
|
|
registered with the EL3 runtime firmware using the
|
|
``register_interrupt_type_handler()`` API as follows
|
|
|
|
.. code:: c
|
|
|
|
/* Forward declaration */
|
|
interrupt_type_handler tspd_ns_interrupt_handler;
|
|
int32_t rc, flags = 0;
|
|
set_interrupt_rm_flag(flags, SECURE);
|
|
rc = register_interrupt_type_handler(INTR_TYPE_NS,
|
|
tspd_ns_interrupt_handler,
|
|
flags);
|
|
if (rc)
|
|
panic();
|
|
|
|
Secure payload
|
|
~~~~~~~~~~~~~~
|
|
|
|
A Secure Payload must implement an interrupt handling framework at Secure-EL1
|
|
(Secure-EL1 IHF) to support its chosen interrupt routing model. Secure payload
|
|
execution will alternate between the below cases.
|
|
|
|
#. In the code where IRQ, FIQ or both interrupts are enabled, if an interrupt
|
|
type is targeted to the FEL, then it will be routed to the Secure-EL1
|
|
exception vector table. This is defined as the **asynchronous mode** of
|
|
handling interrupts. This mode applies to both Secure-EL1 and non-secure
|
|
interrupts.
|
|
|
|
#. In the code where both interrupts are disabled, if an interrupt type is
|
|
targeted to the FEL, then execution will eventually migrate to the
|
|
non-secure state. Any non-secure interrupts will be handled as described
|
|
in the routing model where **CSS=1 and TEL3=0**. Secure-EL1 interrupts
|
|
will be routed to EL3 (as per the routing model where **CSS=1 and
|
|
TEL3=1**) where the SPD service will hand them to the SP. This is defined
|
|
as the **synchronous mode** of handling interrupts.
|
|
|
|
The interrupt handling framework implemented by the SP should support one or
|
|
both these interrupt handling models depending upon the chosen routing model.
|
|
|
|
The following list briefly describes how the choice of a valid routing model
|
|
(See 1.2.3) effects the implementation of the Secure-EL1 IHF. If the choice of
|
|
the interrupt routing model is not known to the SPD service at compile time,
|
|
then the SP should pass this information to the SPD service at runtime during
|
|
its initialisation phase.
|
|
|
|
As mentioned earlier, a ARM GICv2 system is considered and it is assumed that
|
|
the FIQ signal is used to generate Secure-EL1 interrupts and the IRQ signal
|
|
is used to generate non-secure interrupts in either security state.
|
|
|
|
Secure payload IHF design w.r.t secure-EL1 interrupts
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
#. **CSS=0, TEL3=0**. If ``PSTATE.F=0``, Secure-EL1 interrupts will be
|
|
triggered at one of the Secure-EL1 FIQ exception vectors. The Secure-EL1
|
|
IHF should implement support for handling FIQ interrupts asynchronously.
|
|
|
|
If ``PSTATE.F=1`` then Secure-EL1 interrupts will be handled as per the
|
|
synchronous interrupt handling model. The SP could implement this scenario
|
|
by exporting a separate entrypoint for Secure-EL1 interrupts to the SPD
|
|
service during the registration phase. The SPD service would also need to
|
|
know the state of the system, general purpose and the ``PSTATE`` registers
|
|
in which it should arrange to return execution to the SP. The SP should
|
|
provide this information in an implementation defined way during the
|
|
registration phase if it is not known to the SPD service at build time.
|
|
|
|
#. **CSS=1, TEL3=1**. Interrupts are routed to EL3 when execution is in
|
|
non-secure state. They should be handled through the synchronous interrupt
|
|
handling model as described in 1. above.
|
|
|
|
#. **CSS=0, TEL3=1**. Secure-EL1 interrupts are routed to EL3 when execution
|
|
is in secure state. They will not be visible to the SP. The ``PSTATE.F`` bit
|
|
in Secure-EL1/Secure-EL0 will not mask FIQs. The EL3 runtime firmware will
|
|
call the handler registered by the SPD service for Secure-EL1 interrupts.
|
|
Secure-EL1 IHF should then handle all Secure-EL1 interrupt through the
|
|
synchronous interrupt handling model described in 1. above.
|
|
|
|
Secure payload IHF design w.r.t non-secure interrupts
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
#. **CSS=0, TEL3=0**. If ``PSTATE.I=0``, non-secure interrupts will be
|
|
triggered at one of the Secure-EL1 IRQ exception vectors . The Secure-EL1
|
|
IHF should co-ordinate with the SPD service to transfer execution to the
|
|
non-secure state where the interrupt should be handled e.g the SP could
|
|
allocate a function identifier to issue a SMC64 or SMC32 to the SPD
|
|
service which indicates that the SP execution has been preempted by a
|
|
non-secure interrupt. If this function identifier is not known to the SPD
|
|
service at compile time then the SP could provide it during the
|
|
registration phase.
|
|
|
|
If ``PSTATE.I=1`` then the non-secure interrupt will pend until execution
|
|
resumes in the non-secure state.
|
|
|
|
#. **CSS=0, TEL3=1**. Non-secure interrupts are routed to EL3. They will not
|
|
be visible to the SP. The ``PSTATE.I`` bit in Secure-EL1/Secure-EL0 will
|
|
have not effect. The SPD service should register a non-secure interrupt
|
|
handler which should save the SP state correctly and resume execution in
|
|
the non-secure state where the interrupt will be handled. The Secure-EL1
|
|
IHF does not need to take any action.
|
|
|
|
#. **CSS=1, TEL3=0**. Non-secure interrupts are handled in the FEL in
|
|
non-secure state (EL1/EL2) and are not visible to the SP. This routing
|
|
model does not affect the SP behavior.
|
|
|
|
A Secure Payload must also ensure that all Secure-EL1 interrupts are correctly
|
|
configured at the interrupt controller by the platform port of the EL3 runtime
|
|
firmware. It should configure any additional Secure-EL1 interrupts which the EL3
|
|
runtime firmware is not aware of through its platform port.
|
|
|
|
Test secure payload behavior
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
The routing model for Secure-EL1 and non-secure interrupts chosen by the TSP is
|
|
described in Section 2.2.2. It is known to the TSPD service at build time.
|
|
|
|
The TSP implements an entrypoint (``tsp_sel1_intr_entry()``) for handling Secure-EL1
|
|
interrupts taken in non-secure state and routed through the TSPD service
|
|
(synchronous handling model). It passes the reference to this entrypoint via
|
|
``tsp_vectors`` to the TSPD service.
|
|
|
|
The TSP also replaces the default exception vector table referenced through the
|
|
``early_exceptions`` variable, with a vector table capable of handling FIQ and IRQ
|
|
exceptions taken at the same (Secure-EL1) exception level. This table is
|
|
referenced through the ``tsp_exceptions`` variable and programmed into the
|
|
VBAR\_EL1. It caters for the asynchronous handling model.
|
|
|
|
The TSP also programs the Secure Physical Timer in the ARM Generic Timer block
|
|
to raise a periodic interrupt (every half a second) for the purpose of testing
|
|
interrupt management across all the software components listed in 2.1
|
|
|
|
Interrupt handling
|
|
------------------
|
|
|
|
This section describes in detail the role of each software component (see
|
|
Section 2.1) in handling an interrupt of a particular type.
|
|
|
|
EL3 runtime firmware
|
|
~~~~~~~~~~~~~~~~~~~~
|
|
|
|
The EL3 runtime firmware populates the IRQ and FIQ exception vectors referenced
|
|
by the ``runtime_exceptions`` variable as follows.
|
|
|
|
#. IRQ and FIQ exceptions taken from the current exception level with
|
|
``SP_EL0`` or ``SP_EL3`` are reported as irrecoverable error conditions. As
|
|
mentioned earlier, EL3 runtime firmware always executes with the
|
|
``PSTATE.I`` and ``PSTATE.F`` bits set.
|
|
|
|
#. The following text describes how the IRQ and FIQ exceptions taken from a
|
|
lower exception level using AArch64 or AArch32 are handled.
|
|
|
|
When an interrupt is generated, the vector for each interrupt type is
|
|
responsible for:
|
|
|
|
#. Saving the entire general purpose register context (x0-x30) immediately
|
|
upon exception entry. The registers are saved in the per-cpu ``cpu_context``
|
|
data structure referenced by the ``SP_EL3``\ register.
|
|
|
|
#. Saving the ``ELR_EL3``, ``SP_EL0`` and ``SPSR_EL3`` system registers in the
|
|
per-cpu ``cpu_context`` data structure referenced by the ``SP_EL3`` register.
|
|
|
|
#. Switching to the C runtime stack by restoring the ``CTX_RUNTIME_SP`` value
|
|
from the per-cpu ``cpu_context`` data structure in ``SP_EL0`` and
|
|
executing the ``msr spsel, #0`` instruction.
|
|
|
|
#. Determining the type of interrupt. Secure-EL1 interrupts will be signaled
|
|
at the FIQ vector. Non-secure interrupts will be signaled at the IRQ
|
|
vector. The platform should implement the following API to determine the
|
|
type of the pending interrupt.
|
|
|
|
.. code:: c
|
|
|
|
uint32_t plat_ic_get_interrupt_type(void);
|
|
|
|
It should return either ``INTR_TYPE_S_EL1`` or ``INTR_TYPE_NS``.
|
|
|
|
#. Determining the handler for the type of interrupt that has been generated.
|
|
The following API has been added for this purpose.
|
|
|
|
.. code:: c
|
|
|
|
interrupt_type_handler get_interrupt_type_handler(uint32_t interrupt_type);
|
|
|
|
It returns the reference to the registered handler for this interrupt
|
|
type. The ``handler`` is retrieved from the ``intr_type_desc_t`` structure as
|
|
described in Section 2. ``NULL`` is returned if no handler has been
|
|
registered for this type of interrupt. This scenario is reported as an
|
|
irrecoverable error condition.
|
|
|
|
#. Calling the registered handler function for the interrupt type generated.
|
|
The ``id`` parameter is set to ``INTR_ID_UNAVAILABLE`` currently. The id along
|
|
with the current security state and a reference to the ``cpu_context_t``
|
|
structure for the current security state are passed to the handler function
|
|
as its arguments.
|
|
|
|
The handler function returns a reference to the per-cpu ``cpu_context_t``
|
|
structure for the target security state.
|
|
|
|
#. Calling ``el3_exit()`` to return from EL3 into a lower exception level in
|
|
the security state determined by the handler routine. The ``el3_exit()``
|
|
function is responsible for restoring the register context from the
|
|
``cpu_context_t`` data structure for the target security state.
|
|
|
|
Secure payload dispatcher
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
Interrupt entry
|
|
^^^^^^^^^^^^^^^
|
|
|
|
The SPD service begins handling an interrupt when the EL3 runtime firmware calls
|
|
the handler function for that type of interrupt. The SPD service is responsible
|
|
for the following:
|
|
|
|
#. Validating the interrupt. This involves ensuring that the interrupt was
|
|
generating according to the interrupt routing model specified by the SPD
|
|
service during registration. It should use the security state of the
|
|
exception level (passed in the ``flags`` parameter of the handler) where
|
|
the interrupt was taken from to determine this. If the interrupt is not
|
|
recognised then the handler should treat it as an irrecoverable error
|
|
condition.
|
|
|
|
A SPD service can register a handler for Secure-EL1 and/or Non-secure
|
|
interrupts. A non-secure interrupt should never be routed to EL3 from
|
|
from non-secure state. Also if a routing model is chosen where Secure-EL1
|
|
interrupts are routed to S-EL1 when execution is in Secure state, then a
|
|
S-EL1 interrupt should never be routed to EL3 from secure state. The handler
|
|
could use the security state flag to check this.
|
|
|
|
#. Determining whether a context switch is required. This depends upon the
|
|
routing model and interrupt type. For non secure and S-EL1 interrupt,
|
|
if the security state of the execution context where the interrupt was
|
|
generated is not the same as the security state required for handling
|
|
the interrupt, a context switch is required. The following 2 cases
|
|
require a context switch from secure to non-secure or vice-versa:
|
|
|
|
#. A Secure-EL1 interrupt taken from the non-secure state should be
|
|
routed to the Secure Payload.
|
|
|
|
#. A non-secure interrupt taken from the secure state should be routed
|
|
to the last known non-secure exception level.
|
|
|
|
The SPD service must save the system register context of the current
|
|
security state. It must then restore the system register context of the
|
|
target security state. It should use the ``cm_set_next_eret_context()`` API
|
|
to ensure that the next ``cpu_context`` to be restored is of the target
|
|
security state.
|
|
|
|
If the target state is secure then execution should be handed to the SP as
|
|
per the synchronous interrupt handling model it implements. A Secure-EL1
|
|
interrupt can be routed to EL3 while execution is in the SP. This implies
|
|
that SP execution can be preempted while handling an interrupt by a
|
|
another higher priority Secure-EL1 interrupt or a EL3 interrupt. The SPD
|
|
service should be able to handle this preemption or manage secure interrupt
|
|
priorities before handing control to the SP.
|
|
|
|
#. Setting the return value of the handler to the per-cpu ``cpu_context`` if
|
|
the interrupt has been successfully validated and ready to be handled at a
|
|
lower exception level.
|
|
|
|
The routing model allows non-secure interrupts to interrupt Secure-EL1 when in
|
|
secure state if it has been configured to do so. The SPD service and the SP
|
|
should implement a mechanism for routing these interrupts to the last known
|
|
exception level in the non-secure state. The former should save the SP context,
|
|
restore the non-secure context and arrange for entry into the non-secure state
|
|
so that the interrupt can be handled.
|
|
|
|
Interrupt exit
|
|
^^^^^^^^^^^^^^
|
|
|
|
When the Secure Payload has finished handling a Secure-EL1 interrupt, it could
|
|
return control back to the SPD service through a SMC32 or SMC64. The SPD service
|
|
should handle this secure monitor call so that execution resumes in the
|
|
exception level and the security state from where the Secure-EL1 interrupt was
|
|
originally taken.
|
|
|
|
Test secure payload dispatcher Secure-EL1 interrupt handling
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
The example TSPD service registers a handler for Secure-EL1 interrupts taken
|
|
from the non-secure state. During execution in S-EL1, the TSPD expects that the
|
|
Secure-EL1 interrupts are handled in S-EL1 by TSP. Its handler
|
|
``tspd_secure_el1_interrupt_handler()`` expects only to be invoked for Secure-EL1
|
|
originating from the non-secure state. It takes the following actions upon being
|
|
invoked.
|
|
|
|
#. It uses the security state provided in the ``flags`` parameter to ensure
|
|
that the secure interrupt originated from the non-secure state. It asserts
|
|
if this is not the case.
|
|
|
|
#. It saves the system register context for the non-secure state by calling
|
|
``cm_el1_sysregs_context_save(NON_SECURE);``.
|
|
|
|
#. It sets the ``ELR_EL3`` system register to ``tsp_sel1_intr_entry`` and sets the
|
|
``SPSR_EL3.DAIF`` bits in the secure CPU context. It sets ``x0`` to
|
|
``TSP_HANDLE_SEL1_INTR_AND_RETURN``. If the TSP was preempted earlier by a non
|
|
secure interrupt during ``yielding`` SMC processing, save the registers that
|
|
will be trashed, which is the ``ELR_EL3`` and ``SPSR_EL3``, in order to be able
|
|
to re-enter TSP for Secure-EL1 interrupt processing. It does not need to
|
|
save any other secure context since the TSP is expected to preserve it
|
|
(see Section 2.2.2.1).
|
|
|
|
#. It restores the system register context for the secure state by calling
|
|
``cm_el1_sysregs_context_restore(SECURE);``.
|
|
|
|
#. It ensures that the secure CPU context is used to program the next
|
|
exception return from EL3 by calling ``cm_set_next_eret_context(SECURE);``.
|
|
|
|
#. It returns the per-cpu ``cpu_context`` to indicate that the interrupt can
|
|
now be handled by the SP. ``x1`` is written with the value of ``elr_el3``
|
|
register for the non-secure state. This information is used by the SP for
|
|
debugging purposes.
|
|
|
|
The figure below describes how the interrupt handling is implemented by the TSPD
|
|
when a Secure-EL1 interrupt is generated when execution is in the non-secure
|
|
state.
|
|
|
|
|Image 1|
|
|
|
|
The TSP issues an SMC with ``TSP_HANDLED_S_EL1_INTR`` as the function identifier to
|
|
signal completion of interrupt handling.
|
|
|
|
The TSPD service takes the following actions in ``tspd_smc_handler()`` function
|
|
upon receiving an SMC with ``TSP_HANDLED_S_EL1_INTR`` as the function identifier:
|
|
|
|
#. It ensures that the call originated from the secure state otherwise
|
|
execution returns to the non-secure state with ``SMC_UNK`` in ``x0``.
|
|
|
|
#. It restores the saved ``ELR_EL3`` and ``SPSR_EL3`` system registers back to
|
|
the secure CPU context (see step 3 above) in case the TSP had been preempted
|
|
by a non secure interrupt earlier.
|
|
|
|
#. It restores the system register context for the non-secure state by
|
|
calling ``cm_el1_sysregs_context_restore(NON_SECURE)``.
|
|
|
|
#. It ensures that the non-secure CPU context is used to program the next
|
|
exception return from EL3 by calling ``cm_set_next_eret_context(NON_SECURE)``.
|
|
|
|
#. ``tspd_smc_handler()`` returns a reference to the non-secure ``cpu_context``
|
|
as the return value.
|
|
|
|
Test secure payload dispatcher non-secure interrupt handling
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
The TSP in Secure-EL1 can be preempted by a non-secure interrupt during
|
|
``yielding`` SMC processing or by a higher priority EL3 interrupt during
|
|
Secure-EL1 interrupt processing. Currently only non-secure interrupts can
|
|
cause preemption of TSP since there are no EL3 interrupts in the
|
|
system.
|
|
|
|
It should be noted that while TSP is preempted, the TSPD only allows entry into
|
|
the TSP either for Secure-EL1 interrupt handling or for resuming the preempted
|
|
``yielding`` SMC in response to the ``TSP_FID_RESUME`` SMC from the normal world.
|
|
(See Section 3).
|
|
|
|
The non-secure interrupt triggered in Secure-EL1 during ``yielding`` SMC processing
|
|
can be routed to either EL3 or Secure-EL1 and is controlled by build option
|
|
``TSP_NS_INTR_ASYNC_PREEMPT`` (see Section 2.2.2.1). If the build option is set,
|
|
the TSPD will set the routing model for the non-secure interrupt to be routed to
|
|
EL3 from secure state i.e. **TEL3=1, CSS=0** and registers
|
|
``tspd_ns_interrupt_handler()`` as the non-secure interrupt handler. The
|
|
``tspd_ns_interrupt_handler()`` on being invoked ensures that the interrupt
|
|
originated from the secure state and disables routing of non-secure interrupts
|
|
from secure state to EL3. This is to prevent further preemption (by a non-secure
|
|
interrupt) when TSP is reentered for handling Secure-EL1 interrupts that
|
|
triggered while execution was in the normal world. The
|
|
``tspd_ns_interrupt_handler()`` then invokes ``tspd_handle_sp_preemption()`` for
|
|
further handling.
|
|
|
|
If the ``TSP_NS_INTR_ASYNC_PREEMPT`` build option is zero (default), the default
|
|
routing model for non-secure interrupt in secure state is in effect
|
|
i.e. **TEL3=0, CSS=0**. During ``yielding`` SMC processing, the IRQ
|
|
exceptions are unmasked i.e. ``PSTATE.I=0``, and a non-secure interrupt will
|
|
trigger at Secure-EL1 IRQ exception vector. The TSP saves the general purpose
|
|
register context and issues an SMC with ``TSP_PREEMPTED`` as the function
|
|
identifier to signal preemption of TSP. The TSPD SMC handler,
|
|
``tspd_smc_handler()``, ensures that the SMC call originated from the
|
|
secure state otherwise execution returns to the non-secure state with
|
|
``SMC_UNK`` in ``x0``. It then invokes ``tspd_handle_sp_preemption()`` for
|
|
further handling.
|
|
|
|
The ``tspd_handle_sp_preemption()`` takes the following actions upon being
|
|
invoked:
|
|
|
|
#. It saves the system register context for the secure state by calling
|
|
``cm_el1_sysregs_context_save(SECURE)``.
|
|
|
|
#. It restores the system register context for the non-secure state by
|
|
calling ``cm_el1_sysregs_context_restore(NON_SECURE)``.
|
|
|
|
#. It ensures that the non-secure CPU context is used to program the next
|
|
exception return from EL3 by calling ``cm_set_next_eret_context(NON_SECURE)``.
|
|
|
|
#. ``SMC_PREEMPTED`` is set in x0 and return to non secure state after
|
|
restoring non secure context.
|
|
|
|
The Normal World is expected to resume the TSP after the ``yielding`` SMC preemption
|
|
by issuing an SMC with ``TSP_FID_RESUME`` as the function identifier (see section 3).
|
|
The TSPD service takes the following actions in ``tspd_smc_handler()`` function
|
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upon receiving this SMC:
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#. It ensures that the call originated from the non secure state. An
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assertion is raised otherwise.
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#. Checks whether the TSP needs a resume i.e check if it was preempted. It
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then saves the system register context for the non-secure state by calling
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``cm_el1_sysregs_context_save(NON_SECURE)``.
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#. Restores the secure context by calling
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``cm_el1_sysregs_context_restore(SECURE)``
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#. It ensures that the secure CPU context is used to program the next
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exception return from EL3 by calling ``cm_set_next_eret_context(SECURE)``.
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#. ``tspd_smc_handler()`` returns a reference to the secure ``cpu_context`` as the
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return value.
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The figure below describes how the TSP/TSPD handle a non-secure interrupt when
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it is generated during execution in the TSP with ``PSTATE.I`` = 0 when the
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``TSP_NS_INTR_ASYNC_PREEMPT`` build flag is 0.
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|Image 2|
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Secure payload
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~~~~~~~~~~~~~~
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The SP should implement one or both of the synchronous and asynchronous
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interrupt handling models depending upon the interrupt routing model it has
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chosen (as described in 2.2.3).
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In the synchronous model, it should begin handling a Secure-EL1 interrupt after
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receiving control from the SPD service at an entrypoint agreed upon during build
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time or during the registration phase. Before handling the interrupt, the SP
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should save any Secure-EL1 system register context which is needed for resuming
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normal execution in the SP later e.g. ``SPSR_EL1,``\ ELR\_EL1\`. After handling the
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interrupt, the SP could return control back to the exception level and security
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state where the interrupt was originally taken from. The SP should use an SMC32
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or SMC64 to ask the SPD service to do this.
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In the asynchronous model, the Secure Payload is responsible for handling
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non-secure and Secure-EL1 interrupts at the IRQ and FIQ vectors in its exception
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vector table when ``PSTATE.I`` and ``PSTATE.F`` bits are 0. As described earlier,
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when a non-secure interrupt is generated, the SP should coordinate with the SPD
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service to pass control back to the non-secure state in the last known exception
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level. This will allow the non-secure interrupt to be handled in the non-secure
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state.
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Test secure payload behavior
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The TSPD hands control of a Secure-EL1 interrupt to the TSP at the
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``tsp_sel1_intr_entry()``. The TSP handles the interrupt while ensuring that the
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handover agreement described in Section 2.2.2.1 is maintained. It updates some
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statistics by calling ``tsp_update_sync_sel1_intr_stats()``. It then calls
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``tsp_common_int_handler()`` which.
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#. Checks whether the interrupt is the secure physical timer interrupt. It
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uses the platform API ``plat_ic_get_pending_interrupt_id()`` to get the
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interrupt number. If it is not the secure physical timer interrupt, then
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that means that a higher priority interrupt has preempted it. Invoke
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``tsp_handle_preemption()`` to handover control back to EL3 by issuing
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an SMC with ``TSP_PREEMPTED`` as the function identifier.
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#. Handles the secure timer interrupt interrupt by acknowledging it using the
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``plat_ic_acknowledge_interrupt()`` platform API, calling
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``tsp_generic_timer_handler()`` to reprogram the secure physical generic
|
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timer and calling the ``plat_ic_end_of_interrupt()`` platform API to signal
|
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end of interrupt processing.
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The TSP passes control back to the TSPD by issuing an SMC64 with
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``TSP_HANDLED_S_EL1_INTR`` as the function identifier.
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The TSP handles interrupts under the asynchronous model as follows.
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#. Secure-EL1 interrupts are handled by calling the ``tsp_common_int_handler()``
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function. The function has been described above.
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#. Non-secure interrupts are handled by by calling the ``tsp_common_int_handler()``
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function which ends up invoking ``tsp_handle_preemption()`` and issuing an
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SMC64 with ``TSP_PREEMPTED`` as the function identifier. Execution resumes at
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the instruction that follows this SMC instruction when the TSPD hands
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control to the TSP in response to an SMC with ``TSP_FID_RESUME`` as the
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function identifier from the non-secure state (see section 2.3.2.4).
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#. .. rubric:: Other considerations
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:name: other-considerations
|
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Implication of preempted SMC on Non-Secure Software
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---------------------------------------------------
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A ``yielding`` SMC call to Secure payload can be preempted by a non-secure
|
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interrupt and the execution can return to the non-secure world for handling
|
|
the interrupt (For details on ``yielding`` SMC refer `SMC calling convention`_).
|
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In this case, the SMC call has not completed its execution and the execution
|
|
must return back to the secure payload to resume the preempted SMC call.
|
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This can be achieved by issuing an SMC call which instructs to resume the
|
|
preempted SMC.
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A ``fast`` SMC cannot be preempted and hence this case will not happen for
|
|
a fast SMC call.
|
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In the Test Secure Payload implementation, ``TSP_FID_RESUME`` is designated
|
|
as the resume SMC FID. It is important to note that ``TSP_FID_RESUME`` is a
|
|
``yielding`` SMC which means it too can be be preempted. The typical non
|
|
secure software sequence for issuing a ``yielding`` SMC would look like this,
|
|
assuming ``P.STATE.I=0`` in the non secure state :
|
|
|
|
.. code:: c
|
|
|
|
int rc;
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rc = smc(TSP_YIELD_SMC_FID, ...); /* Issue a Yielding SMC call */
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/* The pending non-secure interrupt is handled by the interrupt handler
|
|
and returns back here. */
|
|
while (rc == SMC_PREEMPTED) { /* Check if the SMC call is preempted */
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|
rc = smc(TSP_FID_RESUME); /* Issue resume SMC call */
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}
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The ``TSP_YIELD_SMC_FID`` is any ``yielding`` SMC function identifier and the smc()
|
|
function invokes a SMC call with the required arguments. The pending non-secure
|
|
interrupt causes an IRQ exception and the IRQ handler registered at the
|
|
exception vector handles the non-secure interrupt and returns. The return value
|
|
from the SMC call is tested for ``SMC_PREEMPTED`` to check whether it is
|
|
preempted. If it is, then the resume SMC call ``TSP_FID_RESUME`` is issued. The
|
|
return value of the SMC call is tested again to check if it is preempted.
|
|
This is done in a loop till the SMC call succeeds or fails. If a ``yielding``
|
|
SMC is preempted, until it is resumed using ``TSP_FID_RESUME`` SMC and
|
|
completed, the current TSPD prevents any other SMC call from re-entering
|
|
TSP by returning ``SMC_UNK`` error.
|
|
|
|
--------------
|
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|
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*Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.*
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|
|
.. _Porting Guide: ./porting-guide.rst
|
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.. _SMC calling convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
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.. |Image 1| image:: diagrams/sec-int-handling.png?raw=true
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.. |Image 2| image:: diagrams/non-sec-int-handling.png?raw=true
|