mirror of
https://github.com/CTCaer/switch-l4t-atf.git
synced 2024-11-30 21:30:25 +00:00
7e51e887a7
Include the required FMC2 pinmux definition for the NAND management. Change-Id: I80333deacdf3444b2f21f17f2fb5919e569a3591 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
374 lines
9.0 KiB
Plaintext
374 lines
9.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
/*
|
|
* Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved
|
|
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
*/
|
|
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
|
|
|
/ {
|
|
soc {
|
|
pinctrl: pin-controller@50002000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "st,stm32mp157-pinctrl";
|
|
ranges = <0 0x50002000 0xa400>;
|
|
pins-are-numbered;
|
|
|
|
gpioa: gpio@50002000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x0 0x400>;
|
|
clocks = <&rcc GPIOA>;
|
|
st,bank-name = "GPIOA";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiob: gpio@50003000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x1000 0x400>;
|
|
clocks = <&rcc GPIOB>;
|
|
st,bank-name = "GPIOB";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioc: gpio@50004000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x2000 0x400>;
|
|
clocks = <&rcc GPIOC>;
|
|
st,bank-name = "GPIOC";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiod: gpio@50005000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x3000 0x400>;
|
|
clocks = <&rcc GPIOD>;
|
|
st,bank-name = "GPIOD";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioe: gpio@50006000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x4000 0x400>;
|
|
clocks = <&rcc GPIOE>;
|
|
st,bank-name = "GPIOE";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiof: gpio@50007000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x5000 0x400>;
|
|
clocks = <&rcc GPIOF>;
|
|
st,bank-name = "GPIOF";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiog: gpio@50008000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x6000 0x400>;
|
|
clocks = <&rcc GPIOG>;
|
|
st,bank-name = "GPIOG";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioh: gpio@50009000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x7000 0x400>;
|
|
clocks = <&rcc GPIOH>;
|
|
st,bank-name = "GPIOH";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioi: gpio@5000a000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x8000 0x400>;
|
|
clocks = <&rcc GPIOI>;
|
|
st,bank-name = "GPIOI";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioj: gpio@5000b000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x9000 0x400>;
|
|
clocks = <&rcc GPIOJ>;
|
|
st,bank-name = "GPIOJ";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiok: gpio@5000c000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0xa000 0x400>;
|
|
clocks = <&rcc GPIOK>;
|
|
st,bank-name = "GPIOK";
|
|
status = "disabled";
|
|
};
|
|
|
|
fmc_pins_a: fmc-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
|
|
<STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
|
|
<STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
|
|
<STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
|
|
<STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
|
|
<STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
|
|
<STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
|
|
<STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
|
|
<STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
|
|
<STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
|
|
<STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
|
|
<STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
|
|
<STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <1>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qspi_bk1_pins_a: qspi-bk1-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
|
|
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
|
|
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
|
|
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <1>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
|
|
bias-pull-up;
|
|
drive-push-pull;
|
|
slew-rate = <1>;
|
|
};
|
|
};
|
|
|
|
qspi_bk2_pins_a: qspi-bk2-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
|
|
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
|
|
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
|
|
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <1>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
|
|
bias-pull-up;
|
|
drive-push-pull;
|
|
slew-rate = <1>;
|
|
};
|
|
};
|
|
|
|
qspi_clk_pins_a: qspi-clk-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <3>;
|
|
};
|
|
};
|
|
|
|
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
|
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
|
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
|
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
|
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
|
slew-rate = <1>;
|
|
drive-push-pull;
|
|
bias-disable;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
|
slew-rate = <2>;
|
|
drive-push-pull;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
sdmmc1_dir_pins_a: sdmmc1-dir-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
|
|
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
|
|
<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
|
|
slew-rate = <1>;
|
|
drive-push-pull;
|
|
bias-pull-up;
|
|
};
|
|
pins2{
|
|
pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
|
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
|
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
|
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
|
|
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
slew-rate = <1>;
|
|
drive-push-pull;
|
|
bias-pull-up;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
|
|
slew-rate = <2>;
|
|
drive-push-pull;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
sdmmc2_d47_pins_a: sdmmc2-d47-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
|
|
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
|
|
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
|
|
<STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
|
|
slew-rate = <1>;
|
|
drive-push-pull;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
uart4_pins_a: uart4-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
uart4_pins_b: uart4-1 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
uart7_pins_a: uart7-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
usart3_pins_a: usart3-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
|
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
|
|
<STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
usart3_pins_b: usart3-1 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
|
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
|
|
<STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
pinctrl_z: pin-controller-z@54004000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "st,stm32mp157-z-pinctrl";
|
|
ranges = <0 0x54004000 0x400>;
|
|
pins-are-numbered;
|
|
|
|
gpioz: gpio@54004000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0 0x400>;
|
|
clocks = <&rcc GPIOZ>;
|
|
st,bank-name = "GPIOZ";
|
|
st,bank-ioport = <11>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4_pins_a: i2c4-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
|
|
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
|
|
bias-disable;
|
|
drive-open-drain;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|