Soby Mathew 99e58f9e69 Enable SCR_EL3.SIF bit ... This patch enables the SCR_EL3.SIF (Secure Instruction Fetch) bit in BL1 and BL31 common architectural setup code. When in secure state, this disables instruction fetches from Non-secure memory. NOTE: THIS COULD BREAK PLATFORMS THAT HAVE SECURE WORLD CODE EXECUTING FROM NON-SECURE MEMORY, BUT THIS IS CONSIDERED UNLIKELY AND IS A SERIOUS SECURITY RISK. Fixes ARM-Software/tf-issues#372 Change-Id: I684e84b8d523c3b246e9a5fabfa085b6405df319		2016-04-07 16:30:45 +01:00
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bl1	FWU: Add Generic Firmware Update framework support in BL1	2015-12-09 17:41:18 +00:00
bl31	Remove direct usage of __attribute__((foo))	2016-01-14 10:55:17 -08:00
bl32	Enable use of FIQs and IRQs as TSP interrupts	2015-12-04 12:02:12 +00:00
common	Enable SCR_EL3.SIF bit	2016-04-07 16:30:45 +01:00
drivers	Merge pull request #518 from hzhuang1/pl061_gpio_v5	2016-02-22 10:02:29 +00:00
lib	Merge pull request #577 from antonio-nino-diaz-arm/an/remove-xlat-helpers	2016-04-01 17:41:10 +01:00
plat	Modify return type of plat_get_ns_image_entrypoint()	2016-04-01 17:57:18 +01:00
stdlib	cdefs.h: Use __deprecated__ instead of deprecated	2016-01-20 15:45:39 -08:00