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https://github.com/CTCaer/switch-l4t-atf.git
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18f2efd67d
This patch updates the el3_arch_init_common macro so that it fully initialises essential control registers rather then relying on hardware to set the reset values. The context management functions are also updated to fully initialise the appropriate control registers when initialising the non-secure and secure context structures and when preparing to leave EL3 for a lower EL. This gives better alignement with the ARM ARM which states that software must initialise RES0 and RES1 fields with 0 / 1. This patch also corrects the following typos: "NASCR definitions" -> "NSACR definitions" Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc Signed-off-by: David Cunado <david.cunado@arm.com>
124 lines
3.6 KiB
C
124 lines
3.6 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __EP_INFO_H__
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#define __EP_INFO_H__
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#include <param_header.h>
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#include <utils_def.h>
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#define SECURE U(0x0)
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#define NON_SECURE U(0x1)
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#define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the
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* 'entry_point_info' structure at their correct offsets.
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******************************************************************************/
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#define ENTRY_POINT_INFO_PC_OFFSET U(0x08)
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#ifdef AARCH32
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#define ENTRY_POINT_INFO_ARGS_OFFSET U(0x10)
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#else
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#define ENTRY_POINT_INFO_ARGS_OFFSET U(0x18)
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#endif
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/* The following are used to set/get image attributes. */
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#define PARAM_EP_SECURITY_MASK U(0x1)
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#define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK)
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#define SET_SECURITY_STATE(x, security) \
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((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security))
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#define EP_EE_MASK U(0x2)
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#define EP_EE_SHIFT 1
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#define EP_EE_LITTLE U(0x0)
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#define EP_EE_BIG U(0x2)
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#define EP_GET_EE(x) (x & EP_EE_MASK)
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#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee))
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#define EP_ST_MASK U(0x4)
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#define EP_ST_DISABLE U(0x0)
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#define EP_ST_ENABLE U(0x4)
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#define EP_GET_ST(x) (x & EP_ST_MASK)
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#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee))
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#define EP_EXE_MASK U(0x8)
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#define NON_EXECUTABLE U(0x0)
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#define EXECUTABLE U(0x8)
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#define EP_GET_EXE(x) (x & EP_EXE_MASK)
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#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee))
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#define EP_FIRST_EXE_MASK U(0x10)
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#define EP_FIRST_EXE U(0x10)
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#define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK)
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#define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee))
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#ifndef __ASSEMBLY__
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#include <cassert.h>
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#include <types.h>
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typedef struct aapcs64_params {
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u_register_t arg0;
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u_register_t arg1;
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u_register_t arg2;
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u_register_t arg3;
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u_register_t arg4;
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u_register_t arg5;
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u_register_t arg6;
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u_register_t arg7;
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} aapcs64_params_t;
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typedef struct aapcs32_params {
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u_register_t arg0;
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u_register_t arg1;
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u_register_t arg2;
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u_register_t arg3;
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} aapcs32_params_t;
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/*****************************************************************************
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* This structure represents the superset of information needed while
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* switching exception levels. The only two mechanisms to do so are
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* ERET & SMC. Security state is indicated using bit zero of header
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* attribute
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* NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
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* of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
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* processing SMC to jump to BL31.
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*****************************************************************************/
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typedef struct entry_point_info {
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param_header_t h;
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uintptr_t pc;
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uint32_t spsr;
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#ifdef AARCH32
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aapcs32_params_t args;
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#else
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aapcs64_params_t args;
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#endif
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} entry_point_info_t;
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/*
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* Compile time assertions related to the 'entry_point_info' structure to
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* ensure that the assembler and the compiler view of the offsets of
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* the structure members is the same.
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*/
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CASSERT(ENTRY_POINT_INFO_PC_OFFSET ==
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__builtin_offsetof(entry_point_info_t, pc), \
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assert_BL31_pc_offset_mismatch);
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CASSERT(ENTRY_POINT_INFO_ARGS_OFFSET == \
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__builtin_offsetof(entry_point_info_t, args), \
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assert_BL31_args_offset_mismatch);
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CASSERT(sizeof(uintptr_t) ==
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__builtin_offsetof(entry_point_info_t, spsr) - \
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__builtin_offsetof(entry_point_info_t, pc), \
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assert_entrypoint_and_spsr_should_be_adjacent);
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#endif /*__ASSEMBLY__*/
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#endif /* __EP_INFO_H__ */
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