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419e0d262b
This patch adds support for the QEMU virt ARMv8-A target. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
93 lines
2.8 KiB
C
93 lines
2.8 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <bl_common.h>
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#include <gicv2.h>
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#include <interrupt_mgmt.h>
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uint32_t plat_ic_get_pending_interrupt_id(void)
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{
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return gicv2_get_pending_interrupt_id();
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}
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uint32_t plat_ic_get_pending_interrupt_type(void)
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{
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return gicv2_get_pending_interrupt_type();
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}
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uint32_t plat_ic_acknowledge_interrupt(void)
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{
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return gicv2_acknowledge_interrupt();
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}
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uint32_t plat_ic_get_interrupt_type(uint32_t id)
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{
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uint32_t group;
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group = gicv2_get_interrupt_group(id);
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/* Assume that all secure interrupts are S-EL1 interrupts */
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if (!group)
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return INTR_TYPE_S_EL1;
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else
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return INTR_TYPE_NS;
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}
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void plat_ic_end_of_interrupt(uint32_t id)
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{
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gicv2_end_of_interrupt(id);
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}
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uint32_t plat_interrupt_type_to_line(uint32_t type,
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uint32_t security_state)
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{
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assert(type == INTR_TYPE_S_EL1 ||
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type == INTR_TYPE_EL3 ||
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type == INTR_TYPE_NS);
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assert(sec_state_is_valid(security_state));
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/* Non-secure interrupts are signalled on the IRQ line always */
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if (type == INTR_TYPE_NS)
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return __builtin_ctz(SCR_IRQ_BIT);
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/*
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* Secure interrupts are signalled using the IRQ line if the FIQ_EN
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* bit is not set else they are signalled using the FIQ line.
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*/
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if (gicv2_is_fiq_enabled())
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return __builtin_ctz(SCR_FIQ_BIT);
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else
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return __builtin_ctz(SCR_IRQ_BIT);
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}
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