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b75dc0e41c
ARM erratum 855873 applies to all Cortex-A53 CPUs. The recommended workaround is to promote "data cache clean" instructions to "data cache clean and invalidate" instructions. For core revisions of r0p3 and later this can be done by setting a bit in the CPUACTLR_EL1 register, so that hardware takes care of the promotion. As CPUACTLR_EL1 is both IMPLEMENTATION DEFINED and can be trapped to EL3, we set the bit in firmware. Also we dump this register upon crashing to provide more debug information. Enable the workaround for the Juno boards. Change-Id: I3840114291958a406574ab6c49b01a9d9847fec8 Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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| .. | ||
| diagrams | ||
| plat | ||
| spd | ||
| auth-framework.md | ||
| change-log.md | ||
| cpu-specific-build-macros.md | ||
| firmware-design.md | ||
| firmware-update.md | ||
| interrupt-framework-design.md | ||
| platform-migration-guide.md | ||
| porting-guide.md | ||
| psci-lib-integration-guide.md | ||
| psci-pd-tree.md | ||
| reset-design.md | ||
| rt-svc-writers-guide.md | ||
| trusted-board-boot.md | ||
| user-guide.md | ||