Antonio Nino Diaz 3388b38dc3 Set TCR_EL1.EPD1 bit to 1 ... In the S-EL1&0 translation regime we aren't using the higher VA range, whose translation table base address is held in TTBR1_EL1. The bit TCR_EL1.EPD1 can be used to disable translations using TTBR1_EL1, but the code wasn't setting it to 1. Additionally, other fields in TCR1_EL1 associated with the higher VA range (TBI1, TG1, SH1, ORGN1, IRGN1 and A1) weren't set correctly as they were left as 0. In particular, 0 is a reserved value for TG1. Also, TBBR1_EL1 was not explicitly set and its reset value is UNKNOWN. Therefore memory accesses to the higher VA range would result in unpredictable behaviour as a translation table walk would be attempted using an UNKNOWN value in TTBR1_EL1. On the FVP and Juno platforms accessing the higher VA range resulted in a translation fault, but this may not always be the case on all platforms. This patch sets the bit TCR_EL1.EPD1 to 1 so that any kind of unpredictable behaviour is prevented. This bug only affects the AArch64 version of the code, the AArch32 version sets this bit to 1 as expected. Change-Id: I481c000deda5bc33a475631301767b9e0474a303 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>		2017-09-21 11:57:11 +01:00
..
aarch32	xlat lib: Fix some types	2017-07-26 09:28:23 +01:00
aarch64	Set TCR_EL1.EPD1 bit to 1	2017-09-21 11:57:11 +01:00
xlat_tables_common.c	Resolve signed-unsigned comparison issues	2017-06-27 09:57:21 +01:00
xlat_tables_private.h	xlat lib: Reorganize architectural defs	2017-07-25 13:09:00 +01:00