Sandrine Bailleux cdf1408856 FVP: Do not power off secondary CPUs when booting an EL3 payload ... Normally, in the FVP port, secondary CPUs are immediately powered down if they are powered on at reset. However, when booting an EL3 payload, we need to keep them powered on as the requirement is for all CPUs to enter the EL3 payload image. This patch puts them in a holding pen instead of powering them off. Change-Id: I6526a88b907a0ddb820bead72f1d350a99b1692c		2015-11-26 21:32:04 +00:00
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diagrams	PSCI: Add documentation and fix plat_is_my_cpu_primary()	2015-08-13 23:48:07 +01:00
plat	docs: fix the command to compile BL31 on Tegra	2015-08-01 11:14:32 +05:30
spd	Tegra: retrieve BL32's bootargs from bl32_ep_info	2015-07-31 10:26:22 +05:30
auth-framework.md	TBB: add authentication framework documentation	2015-06-25 08:53:27 +01:00
change-log.md	Documentation for version 1.1	2015-02-03 11:43:43 +00:00
cpu-specific-build-macros.md	cortex_a53: Add A53 errata #826319, #836870	2015-08-05 19:58:39 +08:00
firmware-design.md	Re-design bakery lock memory allocation and algorithm	2015-09-11 16:19:21 +01:00
interrupt-framework-design.md	Some minor fixes to interrupt-framework-design.md	2015-08-04 12:20:46 +08:00
platform-migration-guide.md	docs: Fixes to platform-migration-guide.md	2015-08-18 14:59:25 +01:00
porting-guide.md	FVP: Do not power off secondary CPUs when booting an EL3 payload	2015-11-26 21:32:04 +00:00
psci-pd-tree.md	PSCI: Introduce new platform interface to describe topology	2015-08-13 16:28:26 +01:00
rt-svc-writers-guide.md	Documentation for version 1.1	2015-02-03 11:43:43 +00:00
trusted-board-boot.md	TBB: add authentication framework documentation	2015-06-25 08:53:27 +01:00
user-guide.md	Introduce SPIN_ON_BL1_EXIT build flag	2015-11-26 21:31:59 +00:00