mirror of
https://github.com/CTCaer/switch-l4t-atf.git
synced 2024-12-13 21:58:51 +00:00
5014b52dec
Added a public function to read blocks from a current boot partition. switch between partitions has to respect eMMC partition switch timing. Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com> Change-Id: I55b0c910314253e5647486609583fd290dadd30a
245 lines
7.3 KiB
C
245 lines
7.3 KiB
C
/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MMC_H
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#define MMC_H
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#include <stdint.h>
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#include <lib/utils_def.h>
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#define MMC_BLOCK_SIZE U(512)
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#define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1))
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#define MMC_BOOT_CLK_RATE (400 * 1000)
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#define MMC_CMD(_x) U(_x)
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#define MMC_ACMD(_x) U(_x)
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#define OCR_POWERUP BIT(31)
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#define OCR_HCS BIT(30)
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#define OCR_BYTE_MODE (U(0) << 29)
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#define OCR_SECTOR_MODE (U(2) << 29)
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#define OCR_ACCESS_MODE_MASK (U(3) << 29)
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#define OCR_3_5_3_6 BIT(23)
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#define OCR_3_4_3_5 BIT(22)
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#define OCR_3_3_3_4 BIT(21)
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#define OCR_3_2_3_3 BIT(20)
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#define OCR_3_1_3_2 BIT(19)
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#define OCR_3_0_3_1 BIT(18)
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#define OCR_2_9_3_0 BIT(17)
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#define OCR_2_8_2_9 BIT(16)
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#define OCR_2_7_2_8 BIT(15)
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#define OCR_VDD_MIN_2V7 GENMASK(23, 15)
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#define OCR_VDD_MIN_2V0 GENMASK(14, 8)
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#define OCR_VDD_MIN_1V7 BIT(7)
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#define MMC_RSP_48 BIT(0)
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#define MMC_RSP_136 BIT(1) /* 136 bit response */
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#define MMC_RSP_CRC BIT(2) /* expect valid crc */
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#define MMC_RSP_CMD_IDX BIT(3) /* response contains cmd idx */
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#define MMC_RSP_BUSY BIT(4) /* device may be busy */
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/* JEDEC 4.51 chapter 6.12 */
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#define MMC_RESPONSE_R1 (MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC)
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#define MMC_RESPONSE_R1B (MMC_RESPONSE_R1 | MMC_RSP_BUSY)
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#define MMC_RESPONSE_R2 (MMC_RSP_48 | MMC_RSP_136 | MMC_RSP_CRC)
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#define MMC_RESPONSE_R3 (MMC_RSP_48)
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#define MMC_RESPONSE_R4 (MMC_RSP_48)
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#define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
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#define MMC_RESPONSE_R6 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
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#define MMC_RESPONSE_R7 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
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/* Value randomly chosen for eMMC RCA, it should be > 1 */
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#define MMC_FIX_RCA 6
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#define RCA_SHIFT_OFFSET 16
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#define CMD_EXTCSD_PARTITION_CONFIG 179
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#define CMD_EXTCSD_BUS_WIDTH 183
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#define CMD_EXTCSD_HS_TIMING 185
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#define CMD_EXTCSD_PART_SWITCH_TIME 199
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#define CMD_EXTCSD_SEC_CNT 212
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#define EXT_CSD_PART_CONFIG_ACC_MASK GENMASK(2, 0)
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#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3)
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#define PART_CFG_BOOT_PARTITION1_ACCESS (U(1) << 0)
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#define PART_CFG_BOOT_PART_EN_MASK GENMASK(5, 3)
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#define PART_CFG_BOOT_PART_EN_SHIFT 3
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#define PART_CFG_CURRENT_BOOT_PARTITION(x) (((x) & PART_CFG_BOOT_PART_EN_MASK) >> \
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PART_CFG_BOOT_PART_EN_SHIFT)
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/* Values in EXT CSD register */
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#define MMC_BUS_WIDTH_1 U(0)
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#define MMC_BUS_WIDTH_4 U(1)
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#define MMC_BUS_WIDTH_8 U(2)
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#define MMC_BUS_WIDTH_DDR_4 U(5)
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#define MMC_BUS_WIDTH_DDR_8 U(6)
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#define MMC_BOOT_MODE_BACKWARD (U(0) << 3)
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#define MMC_BOOT_MODE_HS_TIMING (U(1) << 3)
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#define MMC_BOOT_MODE_DDR (U(2) << 3)
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#define EXTCSD_SET_CMD (U(0) << 24)
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#define EXTCSD_SET_BITS (U(1) << 24)
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#define EXTCSD_CLR_BITS (U(2) << 24)
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#define EXTCSD_WRITE_BYTES (U(3) << 24)
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#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
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#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
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#define EXTCSD_CMD_SET_NORMAL U(1)
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#define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0)
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#define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3)
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#define CSD_TRAN_SPEED_MULT_SHIFT 3
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#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
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#define STATUS_READY_FOR_DATA BIT(8)
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#define STATUS_SWITCH_ERROR BIT(7)
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#define MMC_GET_STATE(x) (((x) >> 9) & 0xf)
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#define MMC_STATE_IDLE 0
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#define MMC_STATE_READY 1
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#define MMC_STATE_IDENT 2
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#define MMC_STATE_STBY 3
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#define MMC_STATE_TRAN 4
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#define MMC_STATE_DATA 5
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#define MMC_STATE_RCV 6
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#define MMC_STATE_PRG 7
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#define MMC_STATE_DIS 8
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#define MMC_STATE_BTST 9
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#define MMC_STATE_SLP 10
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#define MMC_FLAG_CMD23 (U(1) << 0)
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#define CMD8_CHECK_PATTERN U(0xAA)
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#define VHS_2_7_3_6_V BIT(8)
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#define SD_SCR_BUS_WIDTH_1 BIT(8)
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#define SD_SCR_BUS_WIDTH_4 BIT(10)
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struct mmc_cmd {
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unsigned int cmd_idx;
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unsigned int cmd_arg;
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unsigned int resp_type;
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unsigned int resp_data[4];
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};
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struct mmc_ops {
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void (*init)(void);
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int (*send_cmd)(struct mmc_cmd *cmd);
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int (*set_ios)(unsigned int clk, unsigned int width);
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int (*prepare)(int lba, uintptr_t buf, size_t size);
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int (*read)(int lba, uintptr_t buf, size_t size);
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int (*write)(int lba, const uintptr_t buf, size_t size);
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};
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struct mmc_csd_emmc {
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unsigned int not_used: 1;
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unsigned int crc: 7;
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unsigned int ecc: 2;
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unsigned int file_format: 2;
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unsigned int tmp_write_protect: 1;
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unsigned int perm_write_protect: 1;
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unsigned int copy: 1;
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unsigned int file_format_grp: 1;
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unsigned int reserved_1: 5;
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unsigned int write_bl_partial: 1;
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unsigned int write_bl_len: 4;
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unsigned int r2w_factor: 3;
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unsigned int default_ecc: 2;
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unsigned int wp_grp_enable: 1;
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unsigned int wp_grp_size: 5;
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unsigned int erase_grp_mult: 5;
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unsigned int erase_grp_size: 5;
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unsigned int c_size_mult: 3;
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unsigned int vdd_w_curr_max: 3;
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unsigned int vdd_w_curr_min: 3;
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unsigned int vdd_r_curr_max: 3;
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unsigned int vdd_r_curr_min: 3;
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unsigned int c_size_low: 2;
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unsigned int c_size_high: 10;
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unsigned int reserved_2: 2;
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unsigned int dsr_imp: 1;
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unsigned int read_blk_misalign: 1;
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unsigned int write_blk_misalign: 1;
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unsigned int read_bl_partial: 1;
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unsigned int read_bl_len: 4;
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unsigned int ccc: 12;
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unsigned int tran_speed: 8;
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unsigned int nsac: 8;
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unsigned int taac: 8;
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unsigned int reserved_3: 2;
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unsigned int spec_vers: 4;
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unsigned int csd_structure: 2;
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};
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struct mmc_csd_sd_v2 {
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unsigned int not_used: 1;
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unsigned int crc: 7;
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unsigned int reserved_1: 2;
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unsigned int file_format: 2;
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unsigned int tmp_write_protect: 1;
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unsigned int perm_write_protect: 1;
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unsigned int copy: 1;
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unsigned int file_format_grp: 1;
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unsigned int reserved_2: 5;
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unsigned int write_bl_partial: 1;
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unsigned int write_bl_len: 4;
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unsigned int r2w_factor: 3;
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unsigned int reserved_3: 2;
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unsigned int wp_grp_enable: 1;
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unsigned int wp_grp_size: 7;
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unsigned int sector_size: 7;
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unsigned int erase_block_en: 1;
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unsigned int reserved_4: 1;
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unsigned int c_size_low: 16;
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unsigned int c_size_high: 6;
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unsigned int reserved_5: 6;
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unsigned int dsr_imp: 1;
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unsigned int read_blk_misalign: 1;
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unsigned int write_blk_misalign: 1;
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unsigned int read_bl_partial: 1;
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unsigned int read_bl_len: 4;
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unsigned int ccc: 12;
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unsigned int tran_speed: 8;
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unsigned int nsac: 8;
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unsigned int taac: 8;
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unsigned int reserved_6: 6;
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unsigned int csd_structure: 2;
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};
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enum mmc_device_type {
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MMC_IS_EMMC,
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MMC_IS_SD,
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MMC_IS_SD_HC,
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};
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struct mmc_device_info {
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unsigned long long device_size; /* Size of device in bytes */
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unsigned int block_size; /* Block size in bytes */
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unsigned int max_bus_freq; /* Max bus freq in Hz */
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unsigned int ocr_voltage; /* OCR voltage */
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enum mmc_device_type mmc_dev_type; /* Type of MMC */
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};
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size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size);
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size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size);
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size_t mmc_erase_blocks(int lba, size_t size);
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size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
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size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
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size_t mmc_rpmb_erase_blocks(int lba, size_t size);
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size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size);
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int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
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unsigned int width, unsigned int flags,
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struct mmc_device_info *device_info);
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#endif /* MMC_H */
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