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https://github.com/CTCaer/switch-l4t-atf.git
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ea30694561
nand_wait_ready is called with a millisecond delay but the timeout used a micro second. Fixing the conversion in the timeout call. The prototype of the function is also changed to use an unsigned int parameter. Change-Id: Ia3281be7980477dfbfdb842308d35ecd8b926fb8 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
189 lines
4.8 KiB
C
189 lines
4.8 KiB
C
/*
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* Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DRIVERS_RAW_NAND_H
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#define DRIVERS_RAW_NAND_H
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#include <cdefs.h>
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#include <stdint.h>
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#include <drivers/nand.h>
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/* NAND ONFI default value mode 0 in picosecond */
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#define NAND_TADL_MIN 400000UL
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#define NAND_TALH_MIN 20000UL
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#define NAND_TALS_MIN 50000UL
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#define NAND_TAR_MIN 25000UL
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#define NAND_TCCS_MIN 500000UL
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#define NAND_TCEA_MIN 100000UL
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#define NAND_TCEH_MIN 20000UL
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#define NAND_TCH_MIN 20000UL
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#define NAND_TCHZ_MAX 100000UL
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#define NAND_TCLH_MIN 20000UL
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#define NAND_TCLR_MIN 20000UL
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#define NAND_TCLS_MIN 50000UL
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#define NAND_TCOH_MIN 0UL
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#define NAND_TCS_MIN 70000UL
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#define NAND_TDH_MIN 20000UL
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#define NAND_TDS_MIN 40000UL
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#define NAND_TFEAT_MAX 1000000UL
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#define NAND_TIR_MIN 10000UL
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#define NAND_TITC_MIN 1000000UL
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#define NAND_TR_MAX 200000000UL
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#define NAND_TRC_MIN 100000UL
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#define NAND_TREA_MAX 40000UL
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#define NAND_TREH_MIN 30000UL
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#define NAND_TRHOH_MIN 0UL
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#define NAND_TRHW_MIN 200000UL
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#define NAND_TRHZ_MAX 200000UL
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#define NAND_TRLOH_MIN 0UL
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#define NAND_TRP_MIN 50000UL
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#define NAND_TRR_MIN 40000UL
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#define NAND_TRST_MAX 250000000000ULL
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#define NAND_TWB_MAX 200000UL
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#define NAND_TWC_MIN 100000UL
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#define NAND_TWH_MIN 30000UL
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#define NAND_TWHR_MIN 120000UL
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#define NAND_TWP_MIN 50000UL
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#define NAND_TWW_MIN 100000UL
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/* NAND request types */
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#define NAND_REQ_CMD 0x0000U
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#define NAND_REQ_ADDR 0x1000U
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#define NAND_REQ_DATAIN 0x2000U
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#define NAND_REQ_DATAOUT 0x3000U
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#define NAND_REQ_WAIT 0x4000U
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#define NAND_REQ_MASK GENMASK(14, 12)
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#define NAND_REQ_BUS_WIDTH_8 BIT(15)
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#define PARAM_PAGE_SIZE 256
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/* NAND ONFI commands */
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#define NAND_CMD_READ_1ST 0x00U
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#define NAND_CMD_CHANGE_1ST 0x05U
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#define NAND_CMD_READID_SIG_ADDR 0x20U
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#define NAND_CMD_READ_2ND 0x30U
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#define NAND_CMD_STATUS 0x70U
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#define NAND_CMD_READID 0x90U
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#define NAND_CMD_CHANGE_2ND 0xE0U
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#define NAND_CMD_READ_PARAM_PAGE 0xECU
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#define NAND_CMD_RESET 0xFFU
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#define ONFI_REV_21 BIT(3)
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#define ONFI_FEAT_BUS_WIDTH_16 BIT(0)
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#define ONFI_FEAT_EXTENDED_PARAM BIT(7)
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/* NAND ECC type */
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#define NAND_ECC_NONE U(0)
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#define NAND_ECC_HW U(1)
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#define NAND_ECC_ONDIE U(2)
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/* NAND bus width */
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#define NAND_BUS_WIDTH_8 U(0)
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#define NAND_BUS_WIDTH_16 U(1)
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struct nand_req {
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struct nand_device *nand;
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uint16_t type;
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uint8_t *addr;
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unsigned int length;
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unsigned int delay_ms;
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unsigned int inst_delay;
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};
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struct nand_param_page {
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/* Rev information and feature block */
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uint32_t page_sig;
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uint16_t rev;
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uint16_t features;
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uint16_t opt_cmd;
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uint8_t jtg;
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uint8_t train_cmd;
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uint16_t ext_param_length;
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uint8_t nb_param_pages;
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uint8_t reserved1[17];
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/* Manufacturer information */
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uint8_t manufacturer[12];
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uint8_t model[20];
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uint8_t manufacturer_id;
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uint16_t data_code;
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uint8_t reserved2[13];
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/* Memory organization */
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uint32_t bytes_per_page;
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uint16_t spare_per_page;
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uint32_t bytes_per_partial;
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uint16_t spare_per_partial;
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uint32_t num_pages_per_blk;
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uint32_t num_blk_in_lun;
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uint8_t num_lun;
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uint8_t num_addr_cycles;
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uint8_t bit_per_cell;
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uint16_t max_bb_per_lun;
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uint16_t blk_endur;
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uint8_t valid_blk_begin;
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uint16_t blk_enbur_valid;
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uint8_t nb_prog_page;
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uint8_t partial_prog_attr;
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uint8_t nb_ecc_bits;
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uint8_t plane_addr;
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uint8_t mplanes_ops;
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uint8_t ez_nand;
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uint8_t reserved3[12];
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/* Electrical parameters */
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uint8_t io_pin_cap_max;
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uint16_t sdr_timing_mode;
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uint16_t sdr_prog_cache_timing;
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uint16_t tprog;
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uint16_t tbers;
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uint16_t tr;
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uint16_t tccs;
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uint8_t nvddr_timing_mode;
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uint8_t nvddr2_timing_mode;
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uint8_t nvddr_features;
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uint16_t clk_input_cap_typ;
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uint16_t io_pin_cap_typ;
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uint16_t input_pin_cap_typ;
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uint8_t input_pin_cap_max;
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uint8_t drv_strength_support;
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uint16_t tr_max;
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uint16_t tadl;
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uint16_t tr_typ;
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uint8_t reserved4[6];
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/* Vendor block */
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uint16_t vendor_revision;
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uint8_t vendor[88];
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uint16_t crc16;
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} __packed;
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struct nand_ctrl_ops {
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int (*exec)(struct nand_req *req);
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void (*setup)(struct nand_device *nand);
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};
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struct rawnand_device {
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struct nand_device *nand_dev;
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const struct nand_ctrl_ops *ops;
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};
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int nand_raw_init(unsigned long long *size, unsigned int *erase_size);
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int nand_wait_ready(unsigned int delay_ms);
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int nand_read_page_cmd(unsigned int page, unsigned int offset,
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uintptr_t buffer, unsigned int len);
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int nand_change_read_column_cmd(unsigned int offset, uintptr_t buffer,
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unsigned int len);
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void nand_raw_ctrl_init(const struct nand_ctrl_ops *ops);
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/*
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* Platform can implement this to override default raw NAND instance
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* configuration.
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*
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* @device: target raw NAND instance.
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* Return 0 on success, negative value otherwise.
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*/
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int plat_get_raw_nand_data(struct rawnand_device *device);
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#endif /* DRIVERS_RAW_NAND_H */
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