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Varun Wadekar e0d4158c71 Tegra: add tzdram_base to plat_params_from_bl2 struct 
This patch adds another member, tzdram_base, to the plat_params_from_bl2 struct
in order to store the TZDRAM carveout base address used to load the Trusted OS.
The monitor programs the memory controller with the TZDRAM base and size in order
to deny any accesses from the NS world.

Change-Id: If39b8674d548175d7ccb6525c18d196ae8a8506c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-02-22 09:16:34 -08:00
bl1 Introduce unified API to zero memory 2017-02-06 17:01:39 +00:00
bl2 Introduce unified API to zero memory 2017-02-06 17:01:39 +00:00
bl2u Introduce unified API to zero memory 2017-02-06 17:01:39 +00:00
bl31 Introduce unified API to zero memory 2017-02-06 17:01:39 +00:00
bl32 Replace some memset call by zeromem 2017-02-06 17:01:39 +00:00
common Introduce unified API to zero memory 2017-02-06 17:01:39 +00:00
docs Tegra: add tzdram_base to plat_params_from_bl2 struct 2017-02-22 09:16:34 -08:00
drivers Merge pull request #844 from antonio-nino-diaz-arm/an/no-timingsafe 2017-02-20 14:00:05 +00:00
fdts Fix incorrect copyright notices 2016-12-14 14:31:32 +00:00
include cpus: Add support for all Denver variants 2017-02-22 09:16:34 -08:00
lib cpus: Add support for all Denver variants 2017-02-22 09:16:34 -08:00
make_helpers Introduce locking primitives using CAS instruction 2017-02-14 09:26:11 +00:00
plat Tegra: add tzdram_base to plat_params_from_bl2 struct 2017-02-22 09:16:34 -08:00
services Replace some memset call by zeromem 2017-02-06 17:01:39 +00:00
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readme.md

ARM Trusted Firmware - version 1.3

ARM Trusted Firmware provides a reference implementation of secure world software for ARMv8-A, including a [Secure Monitor] TEE-SMC executing at Exception Level 3 (EL3). It implements various ARM interface standards, such as the Power State Coordination Interface (PSCI), Trusted Board Boot Requirements (TBBR, ARM DEN0006C-1) and SMC Calling Convention. As far as possible the code is designed for reuse or porting to other ARMv8-A model and hardware platforms.

ARM will continue development in collaboration with interested parties to provide a full reference implementation of PSCI, TBBR and Secure Monitor code to the benefit of all developers working with ARMv8-A TrustZone technology.

License

The software is provided under a BSD-3-Clause license. Contributions to this project are accepted under the same license with developer sign-off as described in the Contributing Guidelines.

This project contains code from other projects as listed below. The original license text is included in those source files.

  • The stdlib source code is derived from FreeBSD code.

  • The libfdt source code is dual licensed. It is used by this project under the terms of the BSD-2-Clause license.

This Release

This release provides a suitable starting point for productization of secure world boot and runtime firmware, executing in either the AArch32 or AArch64 execution state.

Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from ARM Trusted Firmware.

Functionality

  • Initialization of the secure world (for example, exception vectors, control registers, interrupt controller and interrupts for the platform), before transitioning into the normal world at the Exception Level and Register Width specified by the platform.

  • Library support for CPU specific reset and power down sequences. This includes support for errata workarounds.

  • Drivers for both versions 2.0 and 3.0 of the ARM Generic Interrupt Controller specifications (GICv2 and GICv3). The latter also enables GICv3 hardware systems that do not contain legacy GICv2 support.

  • Drivers to enable standard initialization of ARM System IP, for example Cache Coherent Interconnect (CCI), Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone Controller (TZC).

  • SMC (Secure Monitor Call) handling, conforming to the SMC Calling Convention using an EL3 runtime services framework.

  • PSCI library support for the Secondary CPU Boot, CPU Hotplug, CPU Idle and System Shutdown/Reset/Suspend use-cases. This library is pre-integrated with the provided AArch64 EL3 Runtime Software, and is also suitable for integration into other EL3 Runtime Software.

  • A minimal AArch32 Secure Payload to demonstrate PSCI library integration on platforms with AArch32 EL3 Runtime Software.

  • Secure Monitor library code such as world switching, EL1 context management and interrupt routing. When using the provided AArch64 EL3 Runtime Software, this must be integrated with a Secure-EL1 Payload Dispatcher (SPD) component to customize the interaction with a Secure-EL1 Payload (SP), for example a Secure OS.

  • A Test Secure-EL1 Payload and Dispatcher to demonstrate AArch64 Secure Monitor functionality and Secure-EL1 interaction with PSCI.

  • AArch64 SPDs for the OP-TEE Secure OS and [NVidia Trusted Little Kernel] NVidia TLK.

  • A Trusted Board Boot implementation, conforming to all mandatory TBBR requirements. This includes image authentication using certificates, a Firmware Update (or recovery mode) boot flow, and packaging of the various firmware images into a Firmware Image Package (FIP) to be loaded from non-volatile storage. The TBBR implementation is currently only supported in the AArch64 build.

  • Support for alternative boot flows. Some platforms have their own boot firmware and only require the AArch64 EL3 Runtime Software provided by this project. Other platforms require minimal initialization before booting into an arbitrary EL3 payload.

For a full description of functionality and implementation details, please see the Firmware Design and supporting documentation. The Change Log provides details of changes made since the last release.

Platforms

The AArch64 build of this release has been tested on variants r0, r1 and r2 of the [Juno ARM Development Platform] Juno with Linaro Release 16.06.

The AArch64 build of this release has been tested on the following ARM FVPs (64-bit host machine only, with Linaro Release 16.06):

  • Foundation_Platform (Version 10.1, Build 10.1.32)
  • FVP_Base_AEMv8A-AEMv8A (Version 7.7, Build 0.8.7701)
  • FVP_Base_Cortex-A57x4-A53x4 (Version 7.7, Build 0.8.7701)
  • FVP_Base_Cortex-A57x1-A53x1 (Version 7.7, Build 0.8.7701)
  • FVP_Base_Cortex-A57x2-A53x4 (Version 7.7, Build 0.8.7701)

The AArch32 build of this release has been tested on the following ARM FVPs (64-bit host machine only, with Linaro Release 16.06):

  • FVP_Base_AEMv8A-AEMv8A (Version 7.7, Build 0.8.7701)
  • FVP_Base_Cortex-A32x4 (Version 10.1, Build 10.1.32)

The Foundation FVP can be downloaded free of charge. The Base FVPs can be licensed from ARM: see [www.arm.com/fvp] FVP.

This release also contains the following platform support:

  • MediaTek MT6795 and MT8173 SoCs
  • NVidia T210 and T132 SoCs
  • QEMU emulator
  • RockChip RK3368 and RK3399 SoCs
  • Xilinx Zynq UltraScale + MPSoC

Still to Come

  • AArch32 TBBR support and ongoing TBBR alignment.

  • More platform support.

  • Ongoing support for new architectural features, CPUs and System IP.

  • Ongoing PSCI alignment and feature support.

  • Ongoing security hardening, optimization and quality improvements.

For a full list of detailed issues in the current code, please see the Change Log and the GitHub issue tracker.

Getting Started

Get the Trusted Firmware source code from GitHub.

See the User Guide for instructions on how to install, build and use the Trusted Firmware with the ARM FVPs.

See the Firmware Design for information on how the ARM Trusted Firmware works.

See the Porting Guide as well for information about how to use this software on another ARMv8-A platform.

See the Contributing Guidelines for information on how to contribute to this project and the Acknowledgments file for a list of contributors to the project.

Feedback and support

ARM welcomes any feedback on the Trusted Firmware. Please send feedback using the GitHub issue tracker.

ARM licensees may contact ARM directly via their partner managers.

Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.