Alexei Fedorov e290a8fcbc AArch64: Disable Secure Cycle Counter ... This patch fixes an issue when secure world timing information can be leaked because Secure Cycle Counter is not disabled. For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR_EL0 register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR_EL0.DP bit. 'include\aarch64\arch.h' header file was tided up and new ARMv8.5-PMU related definitions were added. Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>		2019-08-21 15:43:24 +01:00
..
aarch32	Refactor SPSR initialisation code	2019-07-24 12:49:54 +01:00
aarch64	AArch64: Disable Secure Cycle Counter	2019-08-21 15:43:24 +01:00
tbbr	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
bl1_fwu.c	Switch AARCH32/AARCH64 to __aarch64__	2019-08-01 13:45:03 -07:00
bl1_main.c	Switch AARCH32/AARCH64 to __aarch64__	2019-08-01 13:45:03 -07:00
bl1_private.h	Move BL1 and BL2 private defines to bl_common.h	2019-01-15 13:52:32 +00:00
bl1.ld.S	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
bl1.mk	Add support for Branch Target Identification	2019-05-24 14:44:45 +01:00