CTCaer/switch-l4t-atf
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switch-l4t-atf/plat/socionext/synquacer
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Louis Mayencourt f1be00da0b Use correct type when reading SCR register 
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.

Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-01-28 11:10:48 +00:00
..
drivers plat/synquacer: enable SCMI support 2019-03-13 09:54:15 +09:00
include socionext: Unify Platform specific defines for PSCI module 2020-01-24 13:15:26 +00:00
platform.mk Remove dependency between SPM_MM and ENABLE_SPM build flags 2019-12-20 16:03:02 +00:00
sq_bl31_setup.c Remove dependency between SPM_MM and ENABLE_SPM build flags 2019-12-20 16:03:02 +00:00
sq_ccn.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
sq_gicv3.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
sq_helpers.S synquacer: Enable PL011 UART Console 2018-06-21 11:22:32 +05:30
sq_psci.c Use correct type when reading SCR register 2020-01-28 11:10:48 +00:00
sq_spm.c spm-mm: Refactor secure_partition.h and its contents 2019-12-20 16:03:41 +00:00
sq_topology.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
sq_xlat_setup.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00