From 6b521e9e9b43928cdb2ea45bed4f233c90211dd2 Mon Sep 17 00:00:00 2001 From: mothran Date: Mon, 14 Sep 2015 20:03:32 -0700 Subject: [PATCH] update the sparc reg read/write to include o/l/i registers --- qemu/target-sparc/unicorn.c | 12 ++++++++++++ qemu/target-sparc/unicorn64.c | 12 ++++++++++++ regress/sparc_reg.py | 19 +++++++++++++++++++ 3 files changed, 43 insertions(+) diff --git a/qemu/target-sparc/unicorn.c b/qemu/target-sparc/unicorn.c index 02aadd7..93bdffd 100644 --- a/qemu/target-sparc/unicorn.c +++ b/qemu/target-sparc/unicorn.c @@ -51,6 +51,12 @@ int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0]; + else if (regid >= UC_SPARC_REG_O0 && regid <= UC_SPARC_REG_O7) + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[regid - UC_SPARC_REG_O0]; + else if (regid >= UC_SPARC_REG_L0 && regid <= UC_SPARC_REG_L7) + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[8 + regid - UC_SPARC_REG_L0]; + else if (regid >= UC_SPARC_REG_I0 && regid <= UC_SPARC_REG_I7) + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[16 + regid - UC_SPARC_REG_I0]; else { switch(regid) { default: break; @@ -81,6 +87,12 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(uint32_t *)value; + else if (regid >= UC_SPARC_REG_O0 && regid <= UC_SPARC_REG_O7) + SPARC_CPU(uc, mycpu)->env.regwptr[regid - UC_SPARC_REG_O0] = *(uint32_t *)value; + else if (regid >= UC_SPARC_REG_L0 && regid <= UC_SPARC_REG_L7) + SPARC_CPU(uc, mycpu)->env.regwptr[8 + regid - UC_SPARC_REG_L0] = *(uint32_t *)value; + else if (regid >= UC_SPARC_REG_I0 && regid <= UC_SPARC_REG_I7) + SPARC_CPU(uc, mycpu)->env.regwptr[16 + regid - UC_SPARC_REG_I0] = *(uint32_t *)value; else { switch(regid) { default: break; diff --git a/qemu/target-sparc/unicorn64.c b/qemu/target-sparc/unicorn64.c index 6b62695..49428fa 100644 --- a/qemu/target-sparc/unicorn64.c +++ b/qemu/target-sparc/unicorn64.c @@ -34,6 +34,12 @@ int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0]; + else if (regid >= UC_SPARC_REG_O0 && regid <= UC_SPARC_REG_O7) + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[regid - UC_SPARC_REG_O0]; + else if (regid >= UC_SPARC_REG_L0 && regid <= UC_SPARC_REG_L7) + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[8 + regid - UC_SPARC_REG_L0]; + else if (regid >= UC_SPARC_REG_I0 && regid <= UC_SPARC_REG_I7) + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[16 + regid - UC_SPARC_REG_I0]; else { switch(regid) { default: break; @@ -64,6 +70,12 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(uint64_t *)value; + else if (regid >= UC_SPARC_REG_O0 && regid <= UC_SPARC_REG_O7) + SPARC_CPU(uc, mycpu)->env.regwptr[regid - UC_SPARC_REG_O0] = *(uint64_t *)value; + else if (regid >= UC_SPARC_REG_L0 && regid <= UC_SPARC_REG_L7) + SPARC_CPU(uc, mycpu)->env.regwptr[8 + regid - UC_SPARC_REG_L0] = *(uint64_t *)value; + else if (regid >= UC_SPARC_REG_I0 && regid <= UC_SPARC_REG_I7) + SPARC_CPU(uc, mycpu)->env.regwptr[16 + regid - UC_SPARC_REG_I0] = *(uint64_t *)value; else { switch(regid) { default: break; diff --git a/regress/sparc_reg.py b/regress/sparc_reg.py index 7385836..33bb03e 100755 --- a/regress/sparc_reg.py +++ b/regress/sparc_reg.py @@ -6,6 +6,25 @@ from unicorn.sparc_const import * uc = Uc(UC_ARCH_SPARC, UC_MODE_32) uc.reg_write(UC_SPARC_REG_SP, 100) uc.reg_write(UC_SPARC_REG_FP, 100) +uc.reg_write(UC_SPARC_REG_G0, 200) +uc.reg_write(UC_SPARC_REG_O0, 201) +uc.reg_write(UC_SPARC_REG_L0, 202) +uc.reg_write(UC_SPARC_REG_L7, 203) +uc.reg_write(UC_SPARC_REG_I0, 204) + print 'writing sp = 100, fp = 100' print 'sp =', uc.reg_read(UC_SPARC_REG_SP) print 'fp =', uc.reg_read(UC_SPARC_REG_FP) +print 'g0 =', uc.reg_read(UC_SPARC_REG_G0) +print 'o0 =', uc.reg_read(UC_SPARC_REG_O0) +print 'l0 =', uc.reg_read(UC_SPARC_REG_L0) +print 'l7 =', uc.reg_read(UC_SPARC_REG_L7) +print 'i0 =', uc.reg_read(UC_SPARC_REG_I0) + +assert uc.reg_read(UC_SPARC_REG_SP) == 100 +assert uc.reg_read(UC_SPARC_REG_FP) == 100 +assert uc.reg_read(UC_SPARC_REG_G0) == 200 +assert uc.reg_read(UC_SPARC_REG_O0) == 201 +assert uc.reg_read(UC_SPARC_REG_L0) == 202 +assert uc.reg_read(UC_SPARC_REG_L7) == 203 +assert uc.reg_read(UC_SPARC_REG_I0) == 204 \ No newline at end of file