mirror of
https://github.com/DynamoRIO/dynamorio.git
synced 2026-10-12 02:02:04 +00:00
Derek Bruening
d9e2352e9c
The group delimiters @{ and @} in our headers were inside regular C
comments rather than Doxygen comments. This worked fine with doxygen
through 1.8.13; but 1.8.17 and up ignore these group directives. Here
we fix this by adding the extra asterisk.
Fixes #4749
843 lines
33 KiB
Perl
Executable File
843 lines
33 KiB
Perl
Executable File
#!/usr/bin/perl
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# **********************************************************
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# Copyright (c) 2014-2020 Google, Inc. All rights reserved.
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# **********************************************************
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# * Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# * Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# * Neither the name of Google, Inc. nor the names of its contributors may be
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# used to endorse or promote products derived from this software without
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# specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL VMWARE, INC. OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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# DAMAGE.
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# Pass this a set of decoding table files from which to extract
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# INSTR_CREATE_ macro signature information.
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# It will construct the different sets of macros needed for each
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# instruction form.
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# It has assumptions on the precise format of the decoding tables and
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# on the decoding table file names (specifically, that *t32* is Thumb).
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#
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# To run on one opcode:
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#
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# tools/arm_macros_gen.pl -v -o OP_add core/ir/arm/table_{a32,t32}*.[ch]
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#
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# To run on everything:
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#
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# tools/arm_macros_gen.pl core/ir/arm/table_{a32,t32}*.[ch]
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#
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# XXX i#1563: should we swap src and dst for stores and for OP_cdp and
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# other instructions to more closely match the assembly order?
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#
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# XXX i#1563: currently we have "Rd" for the dest of a load but asm
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# has it as "Rt".
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my $verbose = 0;
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die "Usage: $0 [-o OP_<opcode>] <table-files>\n" if ($#ARGV < 1);
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my $single_op = '';
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if ($ARGV[0] eq '-v') {
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shift;
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$verbose++;
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}
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if ($ARGV[0] eq '-o') {
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shift;
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$single_op = shift;
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}
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my @infiles = @ARGV;
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# Must process headers first
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@infiles = sort({return -1 if($a =~ /\.h$/);return 1 if($b =~ /\.h$/); return 0;}
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@infiles);
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foreach $infile (@infiles) {
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print "Processing $infile\n" if ($verbose > 0);
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my $extra_num = 0;
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my $thumb = ($infile =~ /t32/) ? 1 : 0;
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open(INFILE, "< $infile") || die "Couldn't open $file\n";
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while (<INFILE>) {
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print "xxx $_\n" if ($verbose > 2);
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if (/^\s*{(OP_\w+)[ ,]/ && ($single_op eq '' || $single_op eq $1) &&
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$1 ne 'OP_CONTD') {
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my $opc = $1;
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$instance{$opc} = 0 if (!defined($instance{$opc}));
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my $encoding = $_;
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my $flags = '';
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# Get the 5 operands plus the flags and exop chain
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if ($encoding =~ /exop\[(\w+)\]},/) {
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$entry{$opc}[$instance{$opc}]{'exop'} = hex($1);
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}
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$encoding =~ s|/\*dup\*/||;
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$encoding =~ s/^[^"]+"\S+",\s*//;
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$encoding =~ s/,[^,]+,[^,]+}.*$//;
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$encoding =~ s/\s//g;
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if ($encoding =~ /,([^,]+)$/) {
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$flags = $1;
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if ($flags =~ /(xop_\w+)/) {
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$entry{$opc}[$instance{$opc}]{'xop'} = $1;
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}
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$encoding =~ s/,[^,]+$//;
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} else {
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die "Cannot find flags: $_";
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}
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my $opstr = collapse_types($encoding, $infile);
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my @opnds = split(',', $opstr);
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my @dsts = ();
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my @srcs = ();
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push(@dsts, $opnds[0]) unless ($opnds[0] eq 'xx');
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if ($flags =~ /srcX4/) {
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push(@srcs, $opnds[1]) unless ($opnds[1] eq 'xx');
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} else {
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push(@dsts, $opnds[1]) unless ($opnds[1] eq 'xx');
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}
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if ($flags =~ /dstX3/) {
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push(@dsts, $opnds[2]) unless ($opnds[2] eq 'xx');
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} else {
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push(@srcs, $opnds[2]) unless ($opnds[2] eq 'xx');
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}
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push(@srcs, $opnds[3]) unless ($opnds[3] eq 'xx');
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push(@srcs, $opnds[4]) unless ($opnds[4] eq 'xx');
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$entry{$opc}[$instance{$opc}]{'line'} = $_;
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$entry{$opc}[$instance{$opc}]{'encoding'} = $encoding;
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$entry{$opc}[$instance{$opc}]{'opstr'} = $opstr;
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@{$entry{$opc}[$instance{$opc}]{'srcs'}} = @srcs;
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@{$entry{$opc}[$instance{$opc}]{'dsts'}} = @dsts;
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$entry{$opc}[$instance{$opc}]{'file'} = $infile;
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if ($verbose > 0) {
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print "$opstr <== $_";
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}
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$instance{$opc}++;
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} elsif (/^\s*{OP_CONTD/) {
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my $opnds = $_;
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die "Two extra-op lines not supported: $_" unless ($opnds =~ /END_LIST/);
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if ($opnds =~ /",(\s*\w+,\s*\w+,\s*\w+,\s*\w+,\s*\w+,)/) {
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my $encoding = collapse_types($1, $infile);
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my @opnds = split(',', $encoding);
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my @dsts = ();
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my @srcs = ();
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push(@dsts, $opnds[0]) unless ($opnds[0] eq 'xx');
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push(@dsts, $opnds[1]) unless ($opnds[1] eq 'xx');
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push(@srcs, $opnds[2]) unless ($opnds[2] eq 'xx');
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push(@srcs, $opnds[3]) unless ($opnds[3] eq 'xx');
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push(@srcs, $opnds[4]) unless ($opnds[4] eq 'xx');
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# Separate extra-args for Thumb and ARM
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$extra{$thumb}[$extra_num]{'line'} = $_;
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@{$extra{$thumb}[$extra_num]{'srcs'}} = @srcs;
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@{$extra{$thumb}[$extra_num]{'dsts'}} = @dsts;
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} else {
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die "Failed to parse extra-op line $_";
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}
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$extra_num++;
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}
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}
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close(INFILE);
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}
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foreach my $opc (keys %entry) {
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my %sigs = ();
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my $check_list = 0;
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my $shift_variant = '';
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my $shift_arg_str = '';
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my $shift_call_str = '';
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my $arg_str = '';
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for (my $i = 0; $i < @{$entry{$opc}}; $i++) {
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# Get extra args
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my $infile = $entry{$opc}[$i]{'file'};
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my $thumb = ($infile =~ /t32/) ? 1 : 0;
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if (defined($entry{$opc}[$i]{'xop'})) {
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my $xop = $entry{$opc}[$i]{'xop'};
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for (my $j = 0; $j < @{$extra{$thumb}}; $j++) {
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if ($extra{$thumb}[$j]{'line'} =~ /$xop\W/) {
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push(@{$entry{$opc}[$i]{'srcs'}}, @{$extra{$thumb}[$j]{'srcs'}});
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push(@{$entry{$opc}[$i]{'dsts'}}, @{$extra{$thumb}[$j]{'dsts'}});
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}
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}
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} elsif (defined($entry{$opc}[$i]{'exop'})) {
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my $exop = $entry{$opc}[$i]{'exop'};
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push(@{$entry{$opc}[$i]{'srcs'}}, @{$extra{$thumb}[$exop]{'srcs'}});
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push(@{$entry{$opc}[$i]{'dsts'}}, @{$extra{$thumb}[$exop]{'dsts'}});
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}
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}
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# Prefer the ARM register names, as the Thumb ones are often completely
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# different, and it would be a real pain to add another set of
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# fragile, hacky mappings to "semantic names".
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# We want to map from each Thumb encoding to a "similar" ARM encoding.
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# We can't do global reg slots b/c they do vary for wb vs non-wb so we
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# store the ARM reg for each slot per operand count.
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# First, store the ARM reg values:
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my %arm_src = ();
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my %arm_dst = ();
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for (my $i = 0; $i < @{$entry{$opc}}; $i++) {
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if ($entry{$opc}[$i]{'file'} !~ /t32/) {
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my $count = @{$entry{$opc}[$i]{'srcs'}};
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for (my $j = 0; $j < $count; $j++) {
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if ($entry{$opc}[$i]{'srcs'}[$j] =~ /\bR/) {
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if (defined($arm_src{$count}{$j})) {
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die "Src regs for $opc in slot x$count $j do not match: ".
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$arm_src{$count}{$j} ." vs ".
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$entry{$opc}[$i]{'srcs'}[$j] ."\n"
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unless ($arm_src{$count}{$j} eq $entry{$opc}[$i]{'srcs'}[$j]);
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}
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$arm_src{$count}{$j} = $entry{$opc}[$i]{'srcs'}[$j];
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}
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}
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$count = @{$entry{$opc}[$i]{'dsts'}};
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for (my $j = 0; $j < $count; $j++) {
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if ($entry{$opc}[$i]{'dsts'}[$j] =~ /\bR/) {
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if (defined($arm_dst{$j})) {
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die "Dst regs for $opc in slot $j do not match: ".
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$arm_dst{$count}{$j} ." vs ".
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$entry{$opc}[$i]{'dsts'}[$j] ."\n"
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unless ($arm_dst{$count}{$j} eq $entry{$opc}[$i]{'dsts'}[$j]);
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}
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$arm_dst{$count}{$j} = $entry{$opc}[$i]{'dsts'}[$j];
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}
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}
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}
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}
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# Now, substitute the ARM reg values into the corresponding Thumb slots:
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for (my $i = 0; $i < @{$entry{$opc}}; $i++) {
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if ($entry{$opc}[$i]{'file'} =~ /t32/) {
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my $count = @{$entry{$opc}[$i]{'srcs'}};
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for (my $j = 0; $j < $count; $j++) {
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if (($entry{$opc}[$i]{'srcs'}[$j] =~ /\bR/ ||
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$entry{$opc}[$i]{'srcs'}[$j] =~ /\bSPw/) &&
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defined($arm_src{$count}{$j})) {
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print "Setting src $j from ".$entry{$opc}[$i]{'srcs'}[$j].
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" to ". $arm_src{$count}{$j} ."\n" if ($verbose > 1);
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$entry{$opc}[$i]{'srcs'}[$j] = $arm_src{$count}{$j};
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}
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}
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$count = @{$entry{$opc}[$i]{'dsts'}};
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for (my $j = 0; $j < $count; $j++) {
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if (($entry{$opc}[$i]{'dsts'}[$j] =~ /\bR/ ||
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$entry{$opc}[$i]{'dsts'}[$j] =~ /\bSPw/) &&
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defined($arm_dst{$count}{$j})) {
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print "Setting dst $j from ".$entry{$opc}[$i]{'dsts'}[$j].
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" to ". $arm_dst{$count}{$j} ."\n" if ($verbose > 1);
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$entry{$opc}[$i]{'dsts'}[$j] = $arm_dst{$count}{$j};
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}
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}
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}
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}
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for (my $i = 0; $i < @{$entry{$opc}}; $i++) {
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# Create a single-string signature line
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my $sig = join " ",@{$entry{$opc}[$i]{'dsts'}};
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$sig .= "; ";
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$sig .= join " ",@{$entry{$opc}[$i]{'srcs'}};
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# Combine first and consec into single var-arg list
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$sig =~ s/WBd LCd/LCd/;
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$sig =~ s/VBq LCq/LCq/;
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# All types of lists look the same
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$sig =~ s/LX\w+/LX/;
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$sig =~ s/LC\w+/LCx/;
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# We collapse SIMD reg sizes
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$sig =~ s/([VW][A-Z]+)[a-z]+/\1x/g;
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# We use V for everything like AArch64 does (XXX i#1563: could be nice
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# to list the S or D name for asm but we are collapsing sizes...)
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$sig =~ s/W/V/g;
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# Special case vmrs
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$sig =~ s/\bCPSR/RBd/ if ($opc eq 'OP_vmrs');
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# Collapse spsr and cpsr
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$sig =~ s/\bCPSR/statreg/;
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$sig =~ s/\bSPSR/statreg/;
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if (!defined($sigs{$sig})) {
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$sigs{$sig} = $sig;
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$check_list = 1 if ($sig =~ /\bL[XC]/);
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$shift_variant = $sig if (($sig =~ /\ssh2 i/ || $sig =~ /\ssh2 R/) &&
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# only arith srcs, not shifts in mem opnds
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$sig !~ /M/);
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}
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print "Entry #$i: $sig\n" if ($verbose > 0);
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}
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if ($check_list) {
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# Avoid a separate instance for singleton vs list of regs
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my @ksig = keys %sigs;
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foreach my $sig (@ksig) {
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# We have to replace in this direction b/c there can be multiple single reg
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# opnds and we only want the one that lines up w/ the list
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if ($sig =~ /\bLX/) {
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my $sig_singleB = $sig;
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my $sig_singleA = $sig;
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$sig_singleB =~ s/\bLX\w*/VBx/; # V[AB]x only singleton type so far
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$sig_singleA =~ s/\bLX\w*/VAx/; # V[AB]x only singleton type so far
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if (defined($sigs{$sig_singleB})) {
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delete $sigs{$sig_singleB};
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} elsif (defined($sigs{$sig_singleA})) {
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delete $sigs{$sig_singleA};
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}
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}
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}
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}
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my $immed_name = 0;
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my @ksig = keys %sigs;
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if ($#ksig == 1) {
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if (($ksig[0] =~ /\bi/ && $ksig[1] !~ /\bi/) ||
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($ksig[1] =~ /\bi/ && $ksig[0] !~ /\bi/)) {
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# See if have same # args and thus candidate for "Rm_or_immed"
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my @sp0 = $ksig[0] =~ / /g;
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my @sp1 = $ksig[1] =~ / /g;
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if ($#sp0 == $#sp1 &&
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# Rule out FPSCR vs immed (OP_vmrs).
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!($ksig[0] =~ /; FPSCR/ && $ksig[1] =~ /; i/) &&
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!($ksig[0] =~ /; i/ && $ksig[1] =~ /; FPSCR/)) {
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# Distinguished by immed but let's make the macros more versatile
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# by combining into a variable-type "Rm_or_immed" arg rather than
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# naming $name_imm.
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my $newsig;
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$newsig = ($ksig[0] =~ /\bi/) ? $ksig[1] : $ksig[0];
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$newsig =~ s/\s*$/_or_imm/;
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delete $sigs{$ksig[0]};
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delete $sigs{$ksig[1]};
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$sigs{$newsig} = $newsig;
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} else {
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$immed_name = 1;
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}
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}
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}
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if ($shift_variant ne '') {
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# Add a simple version w/o the shifted reg
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my $replaced = 0;
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foreach my $sig (keys %sigs) {
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# When we add a simple reg-reg DR_SHIFT_NONE, and a reg-imm or reg-reg
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# exists, combine them into a variable-type "Rm_or_immed" arg
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# rather than forcing the reg-imm to be $name_imm.
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if ($sig =~ /^R\w+;\s*\bi$/ ||
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$sig =~ /^;\s*R\w+\s*\bi$/ ||
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$sig =~ /^;\s*R\w+\s*R\w+$/ ||
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$sig =~ /^R\w+;\s*R\w+$/ ||
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$sig =~ /^R\w+;\s*R\w+\s*\bi$/ ||
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$sig =~ /^R\w+;\s*R\w+\s*\bR\w+$/) {
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my $newsig = $sig;
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my $with_reg = $shift_variant;
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$with_reg =~ s/\s*sh2\s*\w+$//;
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my $check = $with_reg;
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$check =~ s/R\w+\s*$//;
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if ($newsig =~ /\bi/) {
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$newsig =~ s/\bi\s*$//;
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} else {
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$newsig =~ s/\bR\w+\s*$//;
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}
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die "Unknown shift variant $opc |$shift_variant|: |$check| vs |$newsig|\n"
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unless ($check eq $newsig);
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$newsig = $with_reg . "_or_imm_specialshift";
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delete $sigs{$sig};
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$sigs{$newsig} = $newsig;
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$replaced = 1;
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}
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}
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if (!$replaced) {
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my $newsig = $shift_variant;
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$sigs{$newsig} = $newsig;
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$newsig =~ s/\s*sh2\s*\w+$/_specialshift/;
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$sigs{$newsig} = $newsig;
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}
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}
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foreach my $sig (sort keys %sigs) {
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print "Sig: $sig\n" if ($verbose > 0);
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my $name = $opc;
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$name =~ s/^OP_//;
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# Friendly names for things we don't care about for macro names
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$sig =~ s/\bi\w*/imm/g;
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$sig =~ s/\bj\w*/pc/g;
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$sig =~ s/\bM/mem/g;
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$sig =~ s/\bsh\d/shift/g;
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$sig =~ s/\bSPw/sp/g;
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$sig =~ s/\bCR\w+/cpreg/g;
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# Ordinals for dup names
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$sig =~ s/imm\b(.*)imm\b(.*)imm\b/imm\1imm2\2imm3/;
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$sig =~ s/imm\b(.*)imm\b/imm\1imm2/;
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$sig =~ s/cpreg\b(.*)cpreg\b(.*)cpreg\b/cpreg\1cpreg2\2cpreg3/;
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$sig =~ s/cpreg\b(.*)cpreg\b/cpreg\1cpreg2/;
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# Total arg counts
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my $sig_src = $sig;
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$sig_src =~ s/^.*;//;
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my @count = $sig_src =~ /\w+/g;
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my $num_tot_srcs = scalar @count;
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my $sig_dst = $sig;
|
|
$sig_dst =~ s/;.*$//;
|
|
@count = $sig_dst =~ /\w+/g;
|
|
my $num_tot_dsts = scalar @count;
|
|
|
|
# String for explicit args
|
|
my $esig = $sig;
|
|
|
|
# Look for writeback => name and implicit args
|
|
if ($sig =~ /\bmem/ &&
|
|
($sig =~ /RAw.*;.*RAw/ || $sig =~ /sp;.*sp/) &&
|
|
$num_tot_dsts > 0) {
|
|
# For us, writeback or post-indexed look the same. We have
|
|
# two variants: immed disp or index (possibly shifted) reg.
|
|
if ($sig =~ /;.*RD/) {
|
|
$name .= "_wbreg" unless (scalar(keys %sigs) == 1);
|
|
} elsif ($sig =~ /;.*\bi/) {
|
|
$name .= "_wbimm" unless (scalar(keys %sigs) == 1);
|
|
} else {
|
|
$name .= "_wb" unless (scalar(keys %sigs) == 1);
|
|
}
|
|
if ($sig =~ /sp;.*sp/) {
|
|
$sig =~ s/sp/opnd_create_reg(opnd_get_base(mem))/g;
|
|
$esig =~ s/\s*sp//g;
|
|
} else {
|
|
$sig =~ s/RAw/opnd_create_reg(opnd_get_base(mem))/g;
|
|
$esig =~ s/\s*RAw//g;
|
|
}
|
|
$sig =~ s/RDw/opnd_create_reg_ex(opnd_get_reg(Rm) 0 DR_OPND_SHIFTED)/;
|
|
} elsif ($sig =~ /\bshift R/) {
|
|
$name .= "_shreg";
|
|
$sig =~ s/RDw/opnd_create_reg_ex(opnd_get_reg(Rm) 0 DR_OPND_SHIFTED)/;
|
|
} elsif ($sig =~ /\bshift imm/) {
|
|
$name .= "_shimm";
|
|
$sig =~ s/RDw/opnd_create_reg_ex(opnd_get_reg(Rm) 0 DR_OPND_SHIFTED)/;
|
|
} elsif ($immed_name && $sig =~ /\bimm/) {
|
|
$name .= "_imm";
|
|
} elsif ($sig =~ /\bSPSR/) {
|
|
$name .= "_spsr";
|
|
$sig =~ s/SPSR/opnd_create_reg(DR_REG_SPSR)/g;
|
|
$esig =~ s/\s*SPSR//g;
|
|
} elsif ($sig =~ /\bSPSR/) {
|
|
$name .= "_spsr";
|
|
$sig =~ s/SPSR/opnd_create_reg(DR_REG_SPSR)/g;
|
|
$esig =~ s/\s*SPSR//g;
|
|
} elsif ($sig =~ /RAw RBw; RAw RBw/) {
|
|
# OP_smlal{b,t}{b,t}
|
|
$esig =~ s/; RAw RBw/;/g;
|
|
} elsif ($sig =~ /VC\d._/) {
|
|
# Things like OP_vmull, OP_vmls
|
|
$name .= "_scalar";
|
|
} elsif ($opc eq 'OP_msr' && $sig =~ /\bimm2$/) {
|
|
# Distinguished by immed
|
|
$name .= "_imm";
|
|
} elsif (($opc eq 'OP_msr_priv' || $opc eq 'OP_mrs_priv') &&
|
|
$sig =~ /\bstatreg\b/) {
|
|
# Distinguished by immed
|
|
$name .= "_spsr";
|
|
} elsif ($opc =~ /OP_cpsi/ && $sig =~ /\bimm.*\bimm/) {
|
|
$name .= "_noflags";
|
|
} elsif ($opc =~ /OP_vmov_32$/) {
|
|
if ($sig =~ /V.*;/) {
|
|
$name .= "_g2s";
|
|
} else {
|
|
$name .= "_s2g";
|
|
}
|
|
} elsif ($opc eq 'OP_vmov') {
|
|
# Using C++ function overloads would help here.
|
|
# XXX: could we create a vararg version? But how know #dsts?
|
|
# User passes it in and we add instr_create_Ndst_varsrc()?
|
|
if ($sig =~ /^V\w+;\s*R\w+$/) {
|
|
$name .= "_g2s";
|
|
} elsif ($sig =~ /^R\w+;\s*V\w+$/) {
|
|
$name .= "_s2g";
|
|
} elsif ($sig =~ /^V\w+;\s*R\w+\s*R/) {
|
|
$name .= "_gg2s";
|
|
} elsif ($sig =~ /^R\w+\s*R\w+;\s*V\w+$/) {
|
|
$name .= "_s2gg";
|
|
} elsif ($sig =~ /^V\w+\s*V\w+;\s*R\w+\s*R/) {
|
|
$name .= "_gg2ss";
|
|
} else {
|
|
$name .= "_ss2gg";
|
|
}
|
|
} elsif (($opc =~ /^OP_stc/ || $opc =~ /^OP_ldc/) &&
|
|
$sig eq 'cpreg; mem imm imm2') {
|
|
$name .= "_option";
|
|
} elsif ($esig =~ /RBw; .* RBw$/) {
|
|
# Implicit arg for OP_bfc and OP_bfi
|
|
$esig =~ s/RBw$//;
|
|
} elsif ($esig =~ /mem.*; mem/) {
|
|
# Implicit arg for OP_swp*
|
|
$esig =~ s/^mem//;
|
|
}
|
|
|
|
if ($sig =~ /\bshift\b/) {
|
|
$sig =~ s/\bshift/opnd_add_flags(shift DR_OPND_IS_SHIFT)/;
|
|
}
|
|
|
|
# Hardcoded implicit args:
|
|
# SPw, LSL, and ASR, and the k8, k16, k32 consts are explicit in the asm.
|
|
# LRw for OP_bl is not.
|
|
if ($sig =~ /\bLRw/) {
|
|
$sig =~ s/LRw/opnd_create_reg(DR_REG_LR)/;
|
|
$esig =~ s/\s*LRw//g;
|
|
}
|
|
if ($sig =~ /\bFPSCR/) {
|
|
$sig =~ s/FPSCR/opnd_create_reg(DR_REG_FPSCR)/;
|
|
$esig =~ s/\s*FPSCR//g;
|
|
}
|
|
|
|
# Special docs
|
|
if ($opc eq 'OP_msr' && $sig !~ /imm2/) {
|
|
$sig =~ s/imm/imm_msr/;
|
|
$esig =~ s/imm/imm_msr/;
|
|
}
|
|
|
|
$sig = rename_regs($sig);
|
|
$esig = rename_regs($esig);
|
|
|
|
# List of total (including implicit) args
|
|
my $call_str = $sig;
|
|
$call_str =~ s/;//g;
|
|
$call_str =~ s/\s*$//;
|
|
$call_str =~ s/^\s*//;
|
|
$call_str =~ s/\b(\w+)/, \1/g;
|
|
$call_str =~ s/\b([\w\(\)]+)\s+/\1/g;
|
|
$call_str =~ s/\b([A-Za-z0-9_]+)\b/(\1)/g;
|
|
$call_str =~ s/\((opnd_\w+)\)/\1/g;
|
|
$call_str =~ s/\((\d+)\)/\1/g;
|
|
$call_str =~ s/\((DR_[A-Z_]+)\)/\1/g;
|
|
$call_str =~ s/\(, /(/g;
|
|
$call_str =~ s/\(\((\w+)\)\)/(\1)/g;
|
|
|
|
# List of explicit args
|
|
$arg_str = $esig;
|
|
$arg_str =~ s/;//g;
|
|
$arg_str =~ s/\s*$//g;
|
|
$arg_str =~ s/^\s*//g;
|
|
$arg_str =~ s/\b(\w+)/, \1/g;
|
|
$arg_str =~ s/\b(\w+)\s+/\1/g;
|
|
|
|
my $opc_str = $opc;
|
|
my $func_sfx = '';
|
|
|
|
# List => vararg with list at end of course
|
|
if ($sig =~ /\bL/) {
|
|
# Figure out at which index in src/dst list the vararg should be inserted
|
|
my $idx = 0;
|
|
my @ops = split(' ', $sig);
|
|
for (my $i = 0; $i <= $#ops; $i++) {
|
|
last if ($ops[$i] =~ /^L/);
|
|
$idx++;
|
|
$idx = 0 if ($ops[$i] =~ /;$/);
|
|
}
|
|
$arg_str =~ s/, L\w+//;
|
|
$call_str =~ s/, \(L\w+\)//;
|
|
$arg_str .= ", list_len, ...";
|
|
$call_str .= ", __VA_ARGS__";
|
|
if ($sig =~ /;.*\bL/) {
|
|
$func_sfx = '_varsrc';
|
|
$opc_str .= ", $num_tot_dsts, ".($num_tot_srcs-1);
|
|
} else {
|
|
$func_sfx = '_vardst';
|
|
$opc_str .= ", ".($num_tot_dsts-1).", $num_tot_srcs";
|
|
}
|
|
$opc_str .= ", list_len, $idx";
|
|
$num_tot_dsts = 'N';
|
|
$num_tot_srcs = 'M';
|
|
}
|
|
print " Macro sigs: ($esig) | $sig\n" if ($verbose > 0);
|
|
die "XXXX Duplicate macro $name for |$sig|\n" if (defined($dupcheck{$name}));
|
|
$dupcheck{$name} = 1;
|
|
|
|
if ($sig =~ /_specialshift/ && $sig !~ /_imm_specialshift/) {
|
|
$sig =~ s/_specialshift//;
|
|
$arg_str =~ s/_specialshift//;
|
|
$call_str =~ s/_specialshift/, DR_SHIFT_NONE, 0/;
|
|
}
|
|
if ($sig =~ /_or_imm_specialshift/) {
|
|
$sig =~ s/_specialshift//;
|
|
$arg_str =~ s/_specialshift//;
|
|
$call_str =~ s/_specialshift//;
|
|
$arg_str =~ /\s+(\S+)$/;
|
|
$last_arg = $1;
|
|
my $mac = sprintf "#define INSTR_CREATE_%s(dc%s) \\\n".
|
|
" (opnd_is_reg(%s) ? \\\n".
|
|
" INSTR_CREATE_%s_shimm((dc)%s, \\\n".
|
|
" OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \\\n".
|
|
" instr_create_%sdst_%ssrc%s((dc), %s%s))\n",
|
|
$name, $arg_str, $last_arg, $name, $call_str, $num_tot_dsts,
|
|
$num_tot_srcs, $func_sfx, $opc_str, $call_str;
|
|
push(@{$macro{$arg_str}}, ($mac));
|
|
} else {
|
|
my $mac = sprintf "#define INSTR_CREATE_%s(dc%s) \\\n".
|
|
" instr_create_%sdst_%ssrc%s((dc), %s%s)\n",
|
|
$name, $arg_str, $num_tot_dsts, $num_tot_srcs, $func_sfx,
|
|
$opc_str, $call_str;
|
|
push(@{$macro{$arg_str}}, ($mac));
|
|
}
|
|
}
|
|
}
|
|
|
|
foreach my $args (keys %macro) {
|
|
$order{$args} = order_sig($args);
|
|
}
|
|
|
|
my @order = sort({$order{$a} <=> $order{$b}} keys %macro);
|
|
|
|
my %mapping = ('reg' => 'register',
|
|
'Rd' => 'destination register',
|
|
'Rd2' => 'second destination register',
|
|
'Rn' => 'source register',
|
|
'Rn_or_imm' => 'source register, or integer constant,',
|
|
'Rt' => 'source register',
|
|
'Rt2' => 'second source register',
|
|
'Rm' => 'second source register',
|
|
'Rm_or_imm' => 'second source register, or integer constant,',
|
|
'Ra' => 'third source register',
|
|
'Rs' => 'third source register',
|
|
'Vd' => 'destination SIMD register',
|
|
'Vd2' => 'second destination register',
|
|
'Vn' => 'source SIMD register',
|
|
'Vt' => 'source SIMD register',
|
|
'Vt2' => 'second source SIMD register',
|
|
'Vm' => 'second source SIMD register',
|
|
'Vm2' => 'third source SIMD register',
|
|
'Vm_or_imm' => 'source SIMD register, or integer constant,',
|
|
'Vn_or_imm' => 'source SIMD register, or integer constant,',
|
|
'Vs' => 'third source SIMD register',
|
|
'imm' => 'integer constant',
|
|
'imm_msr' => 'integer constant (typically from OPND_CREATE_INT_MSR*)',
|
|
'imm2' => 'second integer constant',
|
|
'imm3' => 'third integer constant',
|
|
'pc' => 'program counter constant',
|
|
'mem' => 'memory',
|
|
'shift' => 'dr_shift_type_t integer constant',
|
|
'cpreg' => 'coprocessor register',
|
|
'cpreg2' => 'second coprocessor register',
|
|
'cpreg3' => 'third coprocessor register',
|
|
'statreg' => 'status register (usually DR_REG_CPSR)',
|
|
'sp' => 'stack pointer');
|
|
|
|
foreach my $args (@order) {
|
|
print '
|
|
/** @name Signature: ';
|
|
my $sigline = "($args)";
|
|
$sigline =~ s/\(, /(/;
|
|
print $sigline;
|
|
print ' */
|
|
/** @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */
|
|
/**
|
|
* This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and
|
|
* the given explicit operands, automatically supplying any implicit operands.
|
|
* The operands should be listed with destinations first, followed by sources.
|
|
* The ordering within these two groups should follow the conventional
|
|
* assembly ordering.
|
|
* \param dc The void * dcontext used to allocate memory for the instr_t.
|
|
';
|
|
$sigline =~ s/\(//;
|
|
$sigline =~ s/\)//;
|
|
$sigline =~ s/\s*//g;
|
|
my @params = split(',', $sigline);
|
|
my %count;
|
|
my $saw_n = 0;
|
|
foreach my $param (@params) {
|
|
$saw_n = 1 if ($param =~ /[VR]n/);
|
|
my $tomap = $param;
|
|
# Singleton src => no "second"
|
|
$tomap =~ s/m/n/ if ($param =~ /[VR]m/ && !$saw_n);
|
|
if ($tomap eq 'list_len') {
|
|
print " * \\param $param The number of registers in the register list.\n";
|
|
} elsif ($tomap eq '...') {
|
|
print " * \\param $param The register list as separate opnd_t arguments.\n";
|
|
print " * The registers in the list must be in increasing order.\n";
|
|
} else {
|
|
die "XXXX No mapping for $param\n" if (!defined($mapping{$tomap}));
|
|
my $full = $mapping{$tomap};
|
|
$count{$param}++;
|
|
die "XXXX Duplicate name $param\n" unless ($count{$param} == 1);
|
|
print " * \\param $param The $full opnd_t operand.\n";
|
|
}
|
|
}
|
|
print " */\n";
|
|
foreach my $mac (sort @{$macro{$args}}) {
|
|
print $mac;
|
|
}
|
|
print '/** @} */ /* end doxygen group */
|
|
';
|
|
}
|
|
|
|
sub collapse_types($, $)
|
|
{
|
|
my ($str, $infile) = @_;
|
|
$str =~ s/\s//g;
|
|
# Collapse opnds that will look identical to the macro and for which
|
|
# we don't need to distinguish later
|
|
$str =~ s/\bM\w+/M/g;
|
|
$str =~ s/\bn\w+/i/g; # Negative immed == positive
|
|
$str =~ s/\bi\w+/i/g; # Type of immed doesn't matter
|
|
$str =~ s/\bj\w+/j/g; # Type of jump immed doesn't matter
|
|
$str =~ s/\bro2\w*/i/; # Rotate-by
|
|
$str =~ s/\bk\w+/i/; # Hardcoded const => immed (all are explicit in asm)
|
|
$str =~ s/\b(R\w)N(\w)/\1\2/g; # User must negate registers
|
|
$str =~ s/\bLSL/shift/g;
|
|
$str =~ s/\bASR/shift/g;
|
|
$str =~ s/\bL[\dPL]+/L/;
|
|
# Thumb-only rules
|
|
if ($infile =~ /t32/) {
|
|
# This is only there when encoding
|
|
$str =~ s/RA_EQ_D\w+/xx/;
|
|
# We're not adding special macros for implicit regs or for
|
|
# destructive src==dst forms. We assume there's a general form
|
|
# (sometimes only w/ our special DR_SHIFT_NONE implicit) for each.
|
|
$str =~ s/,RV/,RA/; # destructive src => diff name (no special macro for it)
|
|
$str =~ s/^SPw/RBw/;
|
|
$str =~ s/\bSPw/RAw/ unless ($str =~ /\bM/); # don't do this for srs
|
|
$str =~ s/\bPC/RA/;
|
|
# We map Thumb names to the corresponding ARM names
|
|
$str =~ s/sh2_4/sh2/;
|
|
$str =~ s/sh1_21/sh1/;
|
|
$str =~ s/^RCw/RBw/; # T32.W often have RCw as dst
|
|
$str =~ s/\bRU/RD/g;
|
|
$str =~ s/\bRV/RB/g;
|
|
$str =~ s/\bRW/RA/g;
|
|
$str =~ s/\bRX/RD/g;
|
|
$str =~ s/\bRY/RA/g;
|
|
$str =~ s/^RZ/RB/g;
|
|
$str =~ s/\bRZ/RA/g;
|
|
}
|
|
return $str;
|
|
}
|
|
|
|
sub order_sig($)
|
|
{
|
|
my ($a) = @_;
|
|
my $ord = 0;
|
|
$ord += 100000000 if ($a =~ /V/);
|
|
$ord += 10000000 if ($a =~ /cpreg/);
|
|
$ord += 1000000 if ($a =~ /\.\.\./);
|
|
$ord += 100000 if ($a =~ /mem/);
|
|
$ord += 10000 if ($a =~ /shift/);
|
|
$ord += 1000 if ($a =~ /imm/);
|
|
@commas = $a =~ /,/g;
|
|
$ord += 100*@commas;
|
|
for (my $i = 0; $i < length($a); $i++) {
|
|
$ord += ord(substr($a, $i, 1))/(($i+1));
|
|
}
|
|
return $ord;
|
|
}
|
|
|
|
# Should be called after removing implicit regs (writeback regs)
|
|
sub rename_regs($)
|
|
{
|
|
my ($str) = @_;
|
|
if ($str !~ /_or_imm/) {
|
|
# Remove subreg modifiers (can't remove earlier)
|
|
$str =~ s/\b([RV]\w[^E2])\w+/\1/;
|
|
}
|
|
# Try to match assembly names
|
|
# XXX i#1563: currently loads use Rd -- using Rt would add complexity
|
|
# We also have several other breaks from asm.
|
|
if ($str =~ /\b[RV]A.*\b[RV]B.*;/) {
|
|
$str =~ s/\b([RV])A\w/\1d/g; # g is for things like OP_smlalbb
|
|
$str =~ s/\b([RV])B\w/\1d2/g;
|
|
$str =~ s/\b([RV])C\w/\1m/;
|
|
$str =~ s/\bRD\w/Rn/;
|
|
} elsif ($str =~ /\bVC.*\bVC2.*/) { # OP_vmov
|
|
# I'm breaking w/ asm to make things clearer and easier for the
|
|
# docs mapping for what is a dst and which is 1st vs 2nd src:
|
|
if ($str =~ /\bVC.*;/) {
|
|
$str =~ s/\bRA\w/Rt2/;
|
|
$str =~ s/\bRB\w/Rt/;
|
|
$str =~ s/\bVC[^0-9]/Vd/; # asm has Vm, Vm2
|
|
$str =~ s/\bVC2\w/Vd2/;
|
|
} else {
|
|
$str =~ s/\bRA\w/Rd2/; # asm has Rt, Rt2
|
|
$str =~ s/\bRB\w/Rd/;
|
|
$str =~ s/\bVC[^0-9]/Vt/; # asm has Vm, Vm2
|
|
$str =~ s/\bVC2\w/Vt2/;
|
|
}
|
|
} elsif ($str =~ /\bVC.*;.*\bRB.*\bRA/) { # OP_vmov
|
|
# I'm breaking w/ asm to make things clearer and easier for the
|
|
# docs mapping for what is a dst:
|
|
$str =~ s/\bRA\w/Rt2/;
|
|
$str =~ s/\bRB\w/Rt/;
|
|
$str =~ s/\bVC\w/Vd/;
|
|
} elsif ($str =~ /\b[RV]A.*;/) {
|
|
if ($str =~ /\bVA.*;/) {
|
|
$str =~ s/\b([RV])B\w/\1t/;
|
|
} else {
|
|
$str =~ s/\b([RV])B\w/\1a/;
|
|
}
|
|
$str =~ s/\b([RV])A\w/\1d/;
|
|
$str =~ s/\b([RV])C\w/\1m/;
|
|
$str =~ s/\bRD\w/Rn/;
|
|
} elsif ($str =~ /;.*\b[RV]DE.*\b[RV]D2.*/) { # OP_stlexd
|
|
$str =~ s/\b([RV])A\w/\1n/;
|
|
$str =~ s/\b([RV])B\w/\1d/;
|
|
$str =~ s/\bRC\w/Rs/;
|
|
$str =~ s/\b([RV])DE\w/\1t/;
|
|
$str =~ s/\b([RV])D2\w/\1t2/;
|
|
} elsif ($str =~ /\b[RV]BE.*\b[RV]B2.*;/) {
|
|
$str =~ s/\b([RV])A\w/\1n/;
|
|
$str =~ s/\b([RV])BE\w/\1d/;
|
|
$str =~ s/\b([RV])B2\w/\1d2/;
|
|
$str =~ s/\bRC\w/Rs/;
|
|
$str =~ s/\bVC\w/Vm/;
|
|
$str =~ s/\bRD\w/Rm/;
|
|
} elsif ($str =~ /\bRB\w; RD\w RC\w+$/) { # OP_lsl
|
|
$str =~ s/\bRB\w/Rd/;
|
|
$str =~ s/\bRC\w/Rm/;
|
|
$str =~ s/\bRD\w/Rn/;
|
|
} elsif ($str =~ /\b[RV]B.*;/) {
|
|
$str =~ s/\b([RV])A\w/\1n/;
|
|
$str =~ s/\b([RV])B\w/\1d/g;
|
|
$str =~ s/\bRC\w/Rs/;
|
|
$str =~ s/\bVC\w/Vm/;
|
|
$str =~ s/\bRD\w/Rm/;
|
|
} elsif ($str =~ /;.*\b[RV]BE.*\b[RV]B2.*/) {
|
|
$str =~ s/\b([RV])A\w/\1n/;
|
|
$str =~ s/\b([RV])BE\w/\1t/;
|
|
$str =~ s/\b([RV])B2\w/\1t2/;
|
|
$str =~ s/\bRC\w/Rs/;
|
|
$str =~ s/\bVC\w/Vm/;
|
|
$str =~ s/\bRD\w/Rm/;
|
|
} elsif ($str =~ /;.*\b[RV]B.*/) {
|
|
$str =~ s/\b([RV])A\w/\1n/;
|
|
$str =~ s/\b([RV])B\w/\1t/;
|
|
$str =~ s/\bRC\w/Rs/;
|
|
$str =~ s/\bVC\w/Vm/;
|
|
$str =~ s/\bRD\w/Rm/;
|
|
} elsif ($str !~ /\b[RV].*;/ && $str =~ /;.*\b[RV]\w/) {
|
|
# Single regs for post-indexing or small # opnds
|
|
$str =~ s/\b([RV])A\w/\1n/;
|
|
$str =~ s/\b([RV])B\w/\1d/;
|
|
$str =~ s/\bRC\w/Rs/;
|
|
$str =~ s/\bVC\w/Vm/;
|
|
$str =~ s/\bRD\w/Rm/;
|
|
} elsif ($str =~ /\bRC\w; RA\w RD\w$/) {
|
|
$str =~ s/\bRC\w/Rd/;
|
|
$str =~ s/\bRA\w/Rn/;
|
|
$str =~ s/\bRD\w/Rm/;
|
|
} elsif ($str =~ /\b[RV]\w/) {
|
|
die "XXXX No reg mapping for $str\n";
|
|
}
|
|
return $str;
|
|
}
|