mirror of
https://github.com/ptitSeb/box64.git
synced 2024-10-06 19:33:37 +00:00
[RV64_DYNAREC] Added more opcodes for xtheadvector and fixed more issues (#1897)
* [RV64_DYNAREC] Added 1 more opcode for xtheadvector * Disabled more opcodes does not apply to xtheadvector * Added 1 more opcode * Added 1 more opcode * fix
This commit is contained in:
Yang Liu
GitHub
parent
e2492a1426
commit
1c7ac8c761
@ -359,6 +359,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VSUB_VV(q0, q0, v0, VECTOR_UNMASKED);
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break;
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case 0x20:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMOVSXBW Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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@ -371,6 +373,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VMV_V_V(q0, v0);
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break;
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case 0x21:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMOVSXBD Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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@ -387,6 +391,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VMV_V_V(q0, v1);
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break;
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case 0x22:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMOVSXBQ Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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@ -405,6 +411,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VMV_V_V(q0, v0);
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break;
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case 0x23:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMOVSXWD Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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@ -417,6 +425,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VMV_V_V(q0, v0);
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break;
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case 0x24:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMOVSXWQ Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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@ -433,6 +443,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VMV_V_V(q0, v1);
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break;
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case 0x25:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMOVSXDQ Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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@ -445,6 +457,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VMV_V_V(q0, v0);
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break;
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case 0x28:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMULDQ Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1);
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@ -452,7 +466,7 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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GETEX_vector(q1, 0, 0, VECTOR_SEW64);
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d0 = fpu_get_scratch(dyn);
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d1 = fpu_get_scratch(dyn);
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// make sure the alignments before vnclip...
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// make sure the alignments before vnsrl...
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v0 = (q0 & 1) ? fpu_get_scratch_lmul(dyn, VECTOR_LMUL2) : q0;
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v1 = (q1 & 1) ? fpu_get_scratch_lmul(dyn, VECTOR_LMUL2) : q1;
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if (v0 != q0) VMV_V_V(v0, q0);
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@ -465,6 +479,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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if (v0 != q0) VMV_V_V(q0, v0);
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break;
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case 0x2B:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PACKUSDW Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW32, 1);
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@ -484,6 +500,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VSLIDEUP_VI(q0, v0, 4, VECTOR_UNMASKED);
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break;
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case 0x30:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMOVZXBW Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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@ -496,6 +514,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VMV_V_V(q0, v0);
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break;
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case 0x31:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMOVZXBD Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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@ -512,6 +532,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VMV_V_V(q0, v1);
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break;
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case 0x32:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMOVZXBQ Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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@ -530,6 +552,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VMV_V_V(q0, v0);
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break;
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case 0x33:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMOVZXWD Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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@ -542,6 +566,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VMV_V_V(q0, v0);
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break;
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case 0x34:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMOVZXWQ Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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@ -558,6 +584,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VMV_V_V(q0, v1);
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break;
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case 0x35:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: lack of tail undisturbed
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INST_NAME("PMOVZXDQ Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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@ -1096,24 +1124,53 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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}
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break;
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case 0x70:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // lack of vrgatherei16.vv
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INST_NAME("PSHUFD Gx, Ex, Ib");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1);
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GETGX_vector(q0, 1, VECTOR_SEW64);
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GETEX_vector(q1, 0, 0, VECTOR_SEW64);
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GETGX_empty_vector(q0);
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v0 = fpu_get_scratch(dyn);
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tmp64u0 = F8;
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tmp64u0 = ((tmp64u0 >> 6) << 48) | (((tmp64u0 >> 4) & 3) << 32) | (((tmp64u0 >> 2) & 3) << 16) | (tmp64u0 & 3);
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VECTOR_SPLAT_IMM(v0, tmp64u0, x4);
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW32, 1);
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if (q0 == q1) {
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if (rv64_xtheadvector) { // lack of vrgatherei16.vv
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v1 = fpu_get_scratch(dyn);
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VRGATHEREI16_VV(v1, q1, v0, VECTOR_UNMASKED);
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VMV_V_V(q0, v1);
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if (tmp64u0 == 0) {
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VXOR_VV(v0, v0, v0, VECTOR_UNMASKED);
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} else {
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tmp64u1 = (((tmp64u0 >> 6) & 3) << 32) | ((tmp64u0 >> 4) & 3);
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tmp64u0 = (((tmp64u0 >> 2) & 3) << 32) | (tmp64u0 & 3);
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if (tmp64u1 == 0) {
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VXOR_VV(v1, v1, v1, VECTOR_UNMASKED);
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} else {
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MOV64x(x4, tmp64u1);
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VMV_S_X(v1, x4); // clears upper bits!
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}
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if (tmp64u0 == tmp64u1) {
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VSLIDE1UP_VX(v0, v1, x4, VECTOR_UNMASKED);
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} else if (tmp64u0 == 0) {
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VSLIDE1UP_VX(v0, v1, xZR, VECTOR_UNMASKED);
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} else {
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MOV64x(x4, tmp64u0);
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VSLIDE1UP_VX(v0, v1, x4, VECTOR_UNMASKED);
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}
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}
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW32, 1);
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if (q0 == q1) {
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VRGATHER_VV(v1, q1, v0, VECTOR_UNMASKED);
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VMV_V_V(q0, v1);
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} else {
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VRGATHER_VV(q0, q1, v0, VECTOR_UNMASKED);
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}
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} else {
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VRGATHEREI16_VV(q0, q1, v0, VECTOR_UNMASKED);
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tmp64u0 = ((tmp64u0 >> 6) << 48) | (((tmp64u0 >> 4) & 3) << 32) | (((tmp64u0 >> 2) & 3) << 16) | (tmp64u0 & 3);
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VECTOR_SPLAT_IMM(v0, tmp64u0, x4);
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW32, 1);
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if (q0 == q1) {
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v1 = fpu_get_scratch(dyn);
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VRGATHEREI16_VV(v1, q1, v0, VECTOR_UNMASKED);
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VMV_V_V(q0, v1);
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} else {
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VRGATHEREI16_VV(q0, q1, v0, VECTOR_UNMASKED);
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}
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}
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break;
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case 0x71:
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@ -1441,19 +1498,21 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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}
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break;
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case 0xD7:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // TODO: VMASK convertion
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INST_NAME("PMOVMSKB Gd, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1);
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GETGD;
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GETEX_vector(q0, 0, 0, VECTOR_SEW8);
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v0 = fpu_get_scratch(dyn);
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v0 = fpu_get_scratch_lmul(dyn, VECTOR_LMUL8);
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VSRL_VI(v0, q0, 7, VECTOR_UNMASKED);
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if (rv64_xtheadvector) {
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// Force VMASK element size to 1bit
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vector_vsetvli(dyn, ninst, x4, VECTOR_SEW8, VECTOR_LMUL8, 1);
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}
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VMSNE_VX(VMASK, v0, xZR, VECTOR_UNMASKED);
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW16, 1);
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VMV_X_S(gd, VMASK);
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ZEXTH(gd, gd);
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if (!rv64_xtheadvector) { ZEXTH(gd, gd); }
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break;
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case 0xD8:
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case 0xD9:
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@ -1708,8 +1767,6 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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VSLL_VX(q0, q0, x4, VECTOR_UNMASKED);
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break;
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case 0xF5:
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if (rv64_xtheadvector) { DEFAULT_VECTOR; } // lack of vrgatherei16.vv
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INST_NAME("PMADDWD Gx, Ex");
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nextop = F8;
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW16, 1);
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@ -1717,18 +1774,36 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
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GETEX_vector(q1, 0, 0, VECTOR_SEW16);
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v0 = fpu_get_scratch_lmul(dyn, VECTOR_LMUL2);
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v1 = fpu_get_scratch_lmul(dyn, VECTOR_LMUL2);
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VWMUL_VV(v0, q1, q0, VECTOR_UNMASKED);
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d0 = fpu_get_scratch_lmul(dyn, VECTOR_LMUL2); // warning, no more scratches!
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ADDI(x4, xZR, 6);
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VID_V(d0, VECTOR_UNMASKED);
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VSLL_VI(d0, d0, 1, VECTOR_UNMASKED); // times 2
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VMIN_VX(d0, d0, x4, VECTOR_UNMASKED);
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VADD_VI(q0, d0, 1, VECTOR_UNMASKED);
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vector_vsetvli(dyn, ninst, x1, VECTOR_SEW32, VECTOR_LMUL2, 2);
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VRGATHEREI16_VV(v1, v0, d0, VECTOR_UNMASKED); // 6 4 2 0
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VRGATHEREI16_VV(d0, v0, q0, VECTOR_UNMASKED); // 7 5 3 1
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW32, 1);
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VADD_VV(q0, v1, d0, VECTOR_UNMASKED);
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d1 = fpu_get_scratch(dyn); // use this at caution!
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VWMUL_VV(v0, q1, q0, VECTOR_UNMASKED);
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if (rv64_xtheadvector) { // lack of vrgatherei16.vv
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ADDI(x4, xZR, 6);
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vector_vsetvli(dyn, ninst, x1, VECTOR_SEW32, VECTOR_LMUL2, 2);
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VID_V(d0, VECTOR_UNMASKED);
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VSLL_VI(d0, d0, 1, VECTOR_UNMASKED); // times 2
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VMIN_VX(d0, d0, x4, VECTOR_UNMASKED);
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VRGATHER_VV(v1, v0, d0, VECTOR_UNMASKED); // 6 4 2 0
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// out of scratches, go back to lmul1 and vmv....
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vector_vsetvli(dyn, ninst, x1, VECTOR_SEW32, VECTOR_LMUL1, 1);
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VMV_V_V(d1, v1);
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VADD_VI(d0, d0, 1, VECTOR_UNMASKED);
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vector_vsetvli(dyn, ninst, x1, VECTOR_SEW32, VECTOR_LMUL2, 2);
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VRGATHER_VV(v1, v0, d0, VECTOR_UNMASKED); // 7 5 3 1
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW32, 1);
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VADD_VV(q0, v1, d1, VECTOR_UNMASKED);
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} else {
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ADDI(x4, xZR, 6);
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VID_V(d0, VECTOR_UNMASKED);
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VSLL_VI(d0, d0, 1, VECTOR_UNMASKED); // times 2
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VMIN_VX(d0, d0, x4, VECTOR_UNMASKED);
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VADD_VI(q0, d0, 1, VECTOR_UNMASKED);
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vector_vsetvli(dyn, ninst, x1, VECTOR_SEW32, VECTOR_LMUL2, 2);
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VRGATHEREI16_VV(v1, v0, d0, VECTOR_UNMASKED); // 6 4 2 0
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VRGATHEREI16_VV(d0, v0, q0, VECTOR_UNMASKED); // 7 5 3 1
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SET_ELEMENT_WIDTH(x1, VECTOR_SEW32, 1);
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VADD_VV(q0, v1, d0, VECTOR_UNMASKED);
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}
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break;
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case 0xF6:
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INST_NAME("PSADBW Gx, Ex");
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@ -2609,7 +2609,7 @@ int vector_vsetvli(dynarec_rv64_t* dyn, int ninst, int s1, int sew, int vlmul, f
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uint32_t vl = (int)((float)(16 >> sew) * multiple);
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uint32_t vtypei = (sew << (3 - !!rv64_xtheadvector)) | vlmul;
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if (dyn->inst_sew == VECTOR_SEWNA || dyn->inst_vl == 0 || dyn->inst_sew != sew || dyn->inst_vl != vl) {
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if (dyn->inst_sew == VECTOR_SEWNA || dyn->inst_vl == 0 || dyn->inst_sew != sew || dyn->inst_vl != vl || dyn->inst_vlmul != vlmul) {
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if (vl <= 31 && !rv64_xtheadvector) {
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VSETIVLI(xZR, vl, vtypei);
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} else {
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@ -1630,6 +1630,7 @@ f28–31 ft8–11 FP temporaries Caller
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#define VAADDU_VV(vd, vs2, vs1, vm) EMIT(R_type(0b0010000 | (vm), vs2, vs1, 0b010, vd, 0b1010111)) // 001000...........010.....1010111
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#define VASUBU_VV(vd, vs2, vs1, vm) EMIT(R_type(0b0010100 | (vm), vs2, vs1, 0b010, vd, 0b1010111)) // 001010...........010.....1010111
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// Warning: zero-extended on xtheadvector!
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#define VMV_X_S(rd, vs2) EMIT(R_type((rv64_xtheadvector ? 0b0011001 : 0b0100001), vs2, 0b00000, 0b010, rd, 0b1010111)) // 0100001.....00000010.....1010111
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// Vector Integer Extension Instructions
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@ -1659,7 +1660,7 @@ f28–31 ft8–11 FP temporaries Caller
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#define VCPOP_M(rd, vs2, vm) EMIT(R_type((rv64_xtheadvector ? 0b0101100 : 0b0100000) | (vm), vs2, 0b10000, 0b010, rd, 0b1010111)) // 010000......10000010.....1010111
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#define VFIRST_M(rd, vs2, vm) EMIT(R_type((rv64_xtheadvector ? 0b0101100 : 0b0100000) | (vm), vs2, 0b10001, 0b010, rd, 0b1010111)) // 010000......10001010.....1010111
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#define VID_V(vd, vm) EMIT(R_type(0b0101000 | (vm), 0b00000, 0b10001, 0b010, vd, 0b1010111)) // 010100.0000010001010.....1010111
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#define VID_V(vd, vm) EMIT(R_type((rv64_xtheadvector ? 0b0101100 : 0b0101000) | (vm), 0b00000, 0b10001, 0b010, vd, 0b1010111)) // 010100.0000010001010.....1010111
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#define VDIVU_VV(vd, vs2, vs1, vm) EMIT(R_type(0b1000000 | (vm), vs2, vs1, 0b010, vd, 0b1010111)) // 100000...........010.....1010111
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#define VDIV_VV(vd, vs2, vs1, vm) EMIT(R_type(0b1000010 | (vm), vs2, vs1, 0b010, vd, 0b1010111)) // 100001...........010.....1010111
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Reference in New Issue
Block a user