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[DYNAREC] Added a experimental BOX64_DYNAREC_WEAKBARRIER option (#2033)
* [DYNAREC] Added a experimental BOX64_DYNAREC_WEAKBARRIER option * Added it to the RCFILE
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d05e719ce3
commit
47dbbe030c
10
src/core.c
10
src/core.c
@ -79,6 +79,7 @@ int box64_dynarec_forced = 0;
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int box64_dynarec_bigblock = 1;
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int box64_dynarec_forward = 128;
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int box64_dynarec_strongmem = 0;
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int box64_dynarec_weakbarrier = 0;
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int box64_dynarec_x87double = 0;
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int box64_dynarec_div0 = 0;
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int box64_dynarec_fastnan = 1;
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@ -785,6 +786,15 @@ void LoadLogEnv()
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if(box64_dynarec_strongmem)
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printf_log(LOG_INFO, "Dynarec will try to emulate a strong memory model%s\n", (box64_dynarec_strongmem==1)?" with limited performance loss":((box64_dynarec_strongmem>1)?" with more performance loss":""));
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}
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p = getenv("BOX64_DYNAREC_WEAKBARRIER");
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if (p) {
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if (strlen(p) == 1) {
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if (p[0] >= '0' && p[0] <= '1')
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box64_dynarec_weakbarrier = p[0] - '0';
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}
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if (box64_dynarec_weakbarrier)
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printf_log(LOG_INFO, "Dynarec will try to use weaker memory barriers to reduce the performance loss introduce by strong memory emulation\n");
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}
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p = getenv("BOX64_DYNAREC_X87DOUBLE");
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if(p) {
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if(strlen(p)==1) {
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@ -489,12 +489,19 @@ int convert_bitmask(uint64_t bitmask);
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// Data Memory Barrier
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#define DMB_gen(CRm) (0b1101010100<<22 | 0b011<<16 | 0b0011<<12 | (CRm)<<8 | 1<<7 | 0b01<<5 | 0b11111)
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#define DMB_ISH() EMIT(DMB_gen(0b1011))
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#define DMB_ISHLD() EMIT(DMB_gen(0b1001))
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#define DMB_ISHST() EMIT(DMB_gen(0b1010))
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#define DMB_LD() EMIT(DMB_gen(0b1101))
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#define DMB_ST() EMIT(DMB_gen(0b1110))
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#define DMB_SY() EMIT(DMB_gen(0b1111))
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// Data Synchronization Barrier
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#define DSB_gen(CRm) (0b1101010100<<22 | 0b011<<16 | 0b0011<<12 | (CRm)<<8 | 1<<7 | 0b00<<5 | 0b11111)
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#define DSB_ISH() EMIT(DSB_gen(0b1011))
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#define DSB_ISHLD() EMIT(DSB_gen(0b1001))
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#define DSB_ISHST() EMIT(DSB_gen(0b1010))
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#define DSB_LD() EMIT(DSB_gen(0b1101))
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#define DSB_ST() EMIT(DSB_gen(0b1110))
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#define DSB_SY() EMIT(DSB_gen(0b1111))
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// Break
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@ -85,7 +85,14 @@
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// End of sequence
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#define SMEND() if(dyn->smwrite && box64_dynarec_strongmem && (box64_dynarec_strongmem!=SMREAD_VAL)) {DMB_ISH();} dyn->smwrite=0; dyn->smread=0
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// Force a Data memory barrier (for LOCK: prefix)
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#define SMDMB() if(box64_dynarec_strongmem){DSB_ISH();}else{DMB_ISH();} dyn->smwrite=0; dyn->smread=0
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#define SMDMB() \
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if (box64_dynarec_strongmem && !box64_dynarec_weakbarrier) { \
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DSB_ISH(); \
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} else { \
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DMB_ISH(); \
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} \
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dyn->smwrite = 0; \
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dyn->smread = 0
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#endif
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@ -27,6 +27,7 @@ extern uintptr_t box64_dynarec_test_start, box64_dynarec_test_end;
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extern int box64_dynarec_bigblock;
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extern int box64_dynarec_forward;
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extern int box64_dynarec_strongmem;
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extern int box64_dynarec_weakbarrier;
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extern int box64_dynarec_fastnan;
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extern int box64_dynarec_fastround;
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extern int box64_dynarec_x87double;
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@ -156,6 +156,7 @@ ENTRYINT(BOX64_DYNAREC_LOG, box64_dynarec_log, 0, 3, 2) \
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ENTRYINT(BOX64_DYNAREC_BIGBLOCK, box64_dynarec_bigblock, 0, 3, 2) \
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ENTRYSTRING_(BOX64_DYNAREC_FORWARD, box64_dynarec_forward) \
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ENTRYINT(BOX64_DYNAREC_STRONGMEM, box64_dynarec_strongmem, 0, 4, 3) \
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ENTRYBOOL(BOX64_DYNAREC_WEAKBARRIER, box64_dynarec_weakbarrier) \
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ENTRYBOOL(BOX64_DYNAREC_X87DOUBLE, box64_dynarec_x87double) \
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ENTRYBOOL(BOX64_DYNAREC_DIV0, box64_dynarec_div0) \
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ENTRYBOOL(BOX64_DYNAREC_FASTNAN, box64_dynarec_fastnan) \
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@ -182,6 +183,7 @@ IGNORE(BOX64_DYNAREC_LOG) \
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IGNORE(BOX64_DYNAREC_BIGBLOCK) \
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IGNORE(BOX64_DYNAREC_FORWARD) \
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IGNORE(BOX64_DYNAREC_STRONGMEM) \
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IGNORE(BOX64_DYNAREC_WEAKBARRIER) \
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IGNORE(BOX64_DYNAREC_X87DOUBLE) \
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IGNORE(BOX64_DYNAREC_DIV0) \
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IGNORE(BOX64_DYNAREC_FASTNAN) \
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