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Added 67.AVX.0F.66 D6 opcode ([ARM64_DYNAREC] too)

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This commit is contained in:
ptitSeb 2024-08-10 09:58:42 +02:00
parent 92531929f3
commit 67af8c2bad
2 changed files with 39 additions and 2 deletions
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21
src/dynarec/arm64/dynarec_arm64_67_avx.c
View File

@ -103,6 +103,27 @@ uintptr_t dynarec64_67_AVX(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int
}
}
else if((vex.m==VEX_M_0F) && (vex.p==VEX_P_66)) {
switch(opcode) {
case 0xD6:
INST_NAME("VMOVQ Ex, Gx");
nextop = F8;
GETG;
v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
if(MODREG) {
v1 = sse_get_reg_empty(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
VMOV(v1, v0);
YMM0((nextop&7)+(rex.b<<3));
} else {
addr = geted32(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0xfff<<3, 7, rex, NULL, 0, 0);
VSTR64_U12(v0, ed, fixedaddress);
}
break;
default:
DEFAULT;
}
}
else {DEFAULT;}
if((*ok==-1) && (box64_dynarec_log>=LOG_INFO || box64_dynarec_dump || box64_dynarec_missing)) {

20
src/emu/x64run67avx.c
View File

@ -76,7 +76,7 @@ uintptr_t Run67AVX(x64emu_t *emu, vex_t vex, uintptr_t addr)
rex_t rex = vex.rex;
if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_F2))
if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_F2)) {
switch(opcode) {
case 0xF6: /* MULX Gd, Vd, Ed (,RDX) */
@ -97,7 +97,23 @@ uintptr_t Run67AVX(x64emu_t *emu, vex_t vex, uintptr_t addr)
default: addr = 0;
}
else addr = 0;
} else if ((vex.m==VEX_M_0F) && (vex.p==VEX_P_66)) {
switch(opcode) {
case 0xD6: /* VMOVQ Ex, Gx */
nextop = F8;
GETEX32(0);
GETGX;
EX->q[0] = GX->q[0];
if(MODREG) {
EX->q[1] = 0;
GETEY;
EY->u128 = 0;
}
break;
default: addr = 0;
}
} else addr = 0;
if(!addr)
printf_log(LOG_INFO, "Unimplemented 67 AVX opcode size %d prefix %s map %s opcode %02X ", 128<<vex.l, avx_prefix_string(vex.p), avx_map_string(vex.m), opcode);