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https://github.com/ptitSeb/box64.git
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[RV64_DYNAREC] Added more opcodes (#712)
* [RV64_DYNAREC] Added 64 33 XOR opcode * [RV64_DYNAREC] Added 0F C8-CF BSWAP opcode * [RV64_DYNAREC] Added 66 0F 3A 0B ROUNDSD opcode * [RV64_DYNAREC] Added F3 0F BC TZCNT opcode * [RV64_DYNAREC] Added F3 0F E6 CVTDQ2PD opcode * [RV64_DYNAREC] Added F3 0F 5B CVTTPS2DQ opcode * [RV64_DYNAREC] Fixed CVTTPS2DQ, CVTDQ2PD and printer
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@ -1003,6 +1003,68 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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SW(x5, gback, 2*4);
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SW(x6, gback, 3*4);
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break;
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case 0xC8:
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case 0xC9:
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case 0xCA:
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case 0xCB:
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case 0xCC:
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case 0xCD:
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case 0xCE:
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case 0xCF: /* BSWAP reg */
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INST_NAME("BSWAP Reg");
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gd = xRAX+(opcode&7)+(rex.b<<3);
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MOV_U12(x1, 0xff);
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SLLI(x4, x1, 8); // mask 0xff00
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if (rex.w) {
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SLLI(x5, x1, 16); // mask 0xff0000
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SLLI(x6, x1, 24); // mask 0xff000000
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SRLI(x2, gd, 56);
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SRLI(x3, gd, 40);
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AND(x3, x3, x4);
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OR(x2, x2, x3);
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SRLI(x3, gd, 24);
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AND(x3, x3, x5);
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OR(x2, x2, x3);
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SRLI(x3, gd, 8);
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AND(x3, x3, x6);
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OR(x2, x2, x3);
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AND(x3, gd, x6);
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SLLI(x3, x3, 8);
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OR(x2, x2, x3);
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AND(x3, gd, x5);
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SLLI(x3, x3, 24);
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OR(x2, x2, x3);
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AND(x3, gd, x4);
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SLLI(x3, x3, 40);
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OR(x2, x2, x3);
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SLLI(x3, x3, 56);
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OR(gd, x2, x3);
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} else {
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SRLIW(x2, gd, 24);
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SRLIW(x3, gd, 8);
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AND(x3, x3, x4);
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OR(x2, x2, x3);
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AND(x3, gd, x4);
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SLLI(x3, x3, 8);
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OR(x2, x2, x3);
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AND(x3, gd, x1);
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SLLI(x3, x3, 24);
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OR(gd, x2, x3);
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}
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break;
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default:
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DEFAULT;
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}
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@ -73,6 +73,17 @@ uintptr_t dynarec64_64(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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GETEDO(x4, 0, x5);
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emit_sub32(dyn, ninst, rex, gd, ed, x3, x4, x5);
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break;
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// case 0x33:
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// INST_NAME("XOR Gd, Seg:Ed");
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// SETFLAGS(X_ALL, SF_SET_PENDING);
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// grab_segdata(dyn, addr, ninst, x4, seg);
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// nextop = F8;
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// GETGD;
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// GETEDO(x4, 0, x5);
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// emit_xor32(dyn, ninst, rex, gd, ed, x3, x4);
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// break;
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case 0x88:
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INST_NAME("MOV Seg:Eb, Gb");
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grab_segdata(dyn, addr, ninst, x4, seg);
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@ -130,6 +141,7 @@ uintptr_t dynarec64_64(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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SMWRITE2();
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}
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break;
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case 0x8B:
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INST_NAME("MOV Gd, Seg:Ed");
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grab_segdata(dyn, addr, ninst, x4, seg);
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@ -47,6 +47,8 @@ uintptr_t dynarec64_660F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
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MAYUSE(eb1);
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MAYUSE(eb2);
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MAYUSE(j64);
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static const int8_t round_round[] = { RD_RNE, RD_RDN, RD_RUP, RD_RTZ };
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switch(opcode) {
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case 0x10:
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@ -242,6 +244,32 @@ uintptr_t dynarec64_660F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
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DEFAULT;
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}
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break;
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case 0x3A: // these are some more SSSE3+ opcodes
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opcode = F8;
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switch(opcode) {
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case 0x0B:
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INST_NAME("ROUNDSD Gx, Ex, Ib");
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nextop = F8;
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GETGX(x1);
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GETEXSD(d0, 0);
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u8 = F8;
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v1 = fpu_get_scratch(dyn);
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if(u8&4) {
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u8 = sse_setround(dyn, ninst, x4, x2);
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FCVTLD(x5, d0, RD_DYN);
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FCVTDL(v1, x5, RD_DYN);
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x87_restoreround(dyn, ninst, u8);
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} else {
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FCVTLD(x5, d0, round_round[u8&3]);
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FCVTDL(v1, x5, round_round[u8&3]);
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}
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FSD(v1, gback, 0);
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break;
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default:
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DEFAULT;
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}
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break;
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case 0x54:
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INST_NAME("ANDPD Gx, Ex");
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nextop = F8;
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@ -224,7 +224,58 @@ uintptr_t dynarec64_F30F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
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SSE_LOOP_MV_Q2(x3);
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if(!MODREG) SMWRITE2();
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break;
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case 0x5B:
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INST_NAME("CVTTPS2DQ Gx, Ex");
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nextop = F8;
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GETEX(x5, 0) ;
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GETGX(x6);
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v0 = fpu_get_scratch(dyn);
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v1 = fpu_get_scratch(dyn);
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q0 = fpu_get_scratch(dyn);
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q1 = fpu_get_scratch(dyn);
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FLW(v0, x5, 0);
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FLW(v1, x5, 4);
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FLW(q0, x5, 8);
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FLW(q1, x5, 12);
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FCVTWS(x1, v0, RD_RTZ);
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FCVTWS(x2, v1, RD_RTZ);
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FCVTWS(x3, q0, RD_RTZ);
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FCVTWS(x4, q1, RD_RTZ);
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SW(x1, x6, 0);
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SW(x2, x6, 4);
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SW(x3, x6, 8);
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SW(x4, x6, 12);
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break;
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case 0xBC:
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INST_NAME("TZCNT Gd, Ed");
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SETFLAGS(X_ZF, SF_SUBSET);
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SET_DFNONE();
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nextop = F8;
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GETED(0);
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GETGD;
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if(!rex.w && MODREG) {
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AND(x4, ed, xMASK);
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ed = x4;
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}
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BNE_MARK(ed, xZR);
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ANDI(xFlags, xFlags, ~((1<<F_ZF) | (1<<F_CF)));
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ORI(xFlags, xFlags, 1<<F_CF);
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MOV32w(gd, rex.w?64:32);
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B_NEXT_nocond;
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MARK;
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NEG(x2, ed);
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AND(x2, x2, ed);
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TABLE64(x3, 0x03f79d71b4ca8b09ULL);
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MUL(x2, x2, x3);
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SRLI(x2, x2, 64-6);
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TABLE64(x1, (uintptr_t)&deBruijn64tab);
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ADD(x1, x1, x2);
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LBU(gd, x1, 0);
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ANDI(xFlags, xFlags, ~((1<<F_ZF) | (1<<F_CF)));
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BNE(gd, xZR, 4+4);
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ORI(xFlags, xFlags, 1<<F_ZF);
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break;
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case 0xBD:
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INST_NAME("LZCNT Gd, Ed");
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SETFLAGS(X_ZF|X_CF, SF_SUBSET);
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@ -326,6 +377,22 @@ uintptr_t dynarec64_F30F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
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NEG(x2, x2);
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FMVWX(d0, x2);
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break;
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case 0xE6:
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INST_NAME("CVTDQ2PD Gx, Ex");
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nextop = F8;
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GETEX(x1, 0);
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GETGX(x2);
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q0 = fpu_get_scratch(dyn);
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q1 = fpu_get_scratch(dyn);
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LW(x3, x1, 0);
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LW(x4, x1, 4);
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FCVTDW(q0, x3, RD_DYN);
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FCVTDW(q1, x4, RD_DYN);
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FSD(q0, x2, 0);
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FSD(q1, x2, 8);
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break;
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default:
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DEFAULT;
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}
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@ -398,6 +398,7 @@ f28–31 ft8–11 FP temporaries Caller
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#define RD_RMM 0b100
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// In instruction’s rm field, selects dynamic rounding mode;
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#define RD_RM 0b111
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#define RD_DYN RD_RM
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// load single precision from rs1+imm12 to frd
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#define FLW(frd, rs1, imm12) EMIT(I_type(imm12, rs1, 0b010, frd, 0b0000111))
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@ -422,7 +423,7 @@ f28–31 ft8–11 FP temporaries Caller
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// Convert from signed 32bits to Single
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#define FCVTSW(frd, rs1, rm) EMIT(R_type(0b1101000, 0b00000, rs1, rm, frd, 0b1010011))
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// Convert from Single to signed 32bits (trucated)
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#define FCVTWS(rd, frs1, tm) EMIT(R_type(0b1100000, 0b00000, frs1, rm, rd, 0b1010011))
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#define FCVTWS(rd, frs1, rm) EMIT(R_type(0b1100000, 0b00000, frs1, rm, rd, 0b1010011))
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#define FADDS(frd, frs1, frs2) EMIT(R_type(0b0000000, frs2, frs1, 0b000, frd, 0b1010011))
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#define FSUBS(frd, frs1, frs2) EMIT(R_type(0b0000100, frs2, frs1, 0b000, frd, 0b1010011))
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@ -1315,7 +1315,7 @@ const char* rv64_print(uint32_t data, uintptr_t addr)
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insn.name = "fcvt.d.lu";
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break;
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}
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PRINT_xd_fs1();
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PRINT_fd_xs1();
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}
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case 0x70: {
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assert(RS2(data) == 0);
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