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[ARM64_DYNAREC] Fixed potential issues with 0F A3/AB/B3/BB opcodes

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ptitSeb 2024-11-16 14:31:20 +01:00
parent 49a854fa7e
commit 74bed6edcb
2 changed files with 13 additions and 8 deletions
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1
src/dynarec/arm64/arm64_emitter.h
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@ -180,6 +180,7 @@ int convert_bitmask(uint64_t bitmask);
#define ADDx_REG(Rd, Rn, Rm) EMIT(ADDSUB_REG_gen(1, 0, 0, 0b00, Rm, 0, Rn, Rd)) #define ADDx_REG(Rd, Rn, Rm) EMIT(ADDSUB_REG_gen(1, 0, 0, 0b00, Rm, 0, Rn, Rd))
#define ADDSx_REG(Rd, Rn, Rm) FEMIT(ADDSUB_REG_gen(1, 0, 1, 0b00, Rm, 0, Rn, Rd)) #define ADDSx_REG(Rd, Rn, Rm) FEMIT(ADDSUB_REG_gen(1, 0, 1, 0b00, Rm, 0, Rn, Rd))
#define ADDx_REG_LSL(Rd, Rn, Rm, lsl) EMIT(ADDSUB_REG_gen(1, 0, 0, 0b00, Rm, lsl, Rn, Rd)) #define ADDx_REG_LSL(Rd, Rn, Rm, lsl) EMIT(ADDSUB_REG_gen(1, 0, 0, 0b00, Rm, lsl, Rn, Rd))
#define ADDz_REG_LSL(Rd, Rn, Rm, lsl) EMIT(ADDSUB_REG_gen(rex.is32bits?0:1, 0, 0, 0b00, Rm, lsl, Rn, Rd))
#define ADDw_REG(Rd, Rn, Rm) EMIT(ADDSUB_REG_gen(0, 0, 0, 0b00, Rm, 0, Rn, Rd)) #define ADDw_REG(Rd, Rn, Rm) EMIT(ADDSUB_REG_gen(0, 0, 0, 0b00, Rm, 0, Rn, Rd))
#define ADDSw_REG(Rd, Rn, Rm) FEMIT(ADDSUB_REG_gen(0, 0, 1, 0b00, Rm, 0, Rn, Rd)) #define ADDSw_REG(Rd, Rn, Rm) FEMIT(ADDSUB_REG_gen(0, 0, 1, 0b00, Rm, 0, Rn, Rd))
#define ADDw_REG_LSL(Rd, Rn, Rm, lsl) EMIT(ADDSUB_REG_gen(0, 0, 0, 0b00, Rm, lsl, Rn, Rd)) #define ADDw_REG_LSL(Rd, Rn, Rm, lsl) EMIT(ADDSUB_REG_gen(0, 0, 0, 0b00, Rm, lsl, Rn, Rd))

20
src/dynarec/arm64/dynarec_arm64_0f.c
View File

@ -1639,8 +1639,9 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else { } else {
SMREAD(); SMREAD();
addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, NULL, 0, 0); addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, NULL, 0, 0);
ASRx(x1, gd, 5+rex.w); // r1 = (gd>>5) ASRxw(x1, gd, 5+rex.w); // r1 = (gd>>5)
ADDx_REG_LSL(x3, wback, x1, 2+rex.w); //(&ed)+=r1*4; if(!rex.w && !rex.is32bits) {SXTWx(x1, x1);}
ADDz_REG_LSL(x3, wback, x1, 2+rex.w); //(&ed)+=r1*4;
LDxw(x1, x3, fixedaddress); LDxw(x1, x3, fixedaddress);
ed = x1; ed = x1;
} }
@ -1712,8 +1713,9 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else { } else {
SMREAD(); SMREAD();
addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, NULL, 0, 0); addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, NULL, 0, 0);
ASRx(x1, gd, 5+rex.w); // r1 = (gd>>5) ASRxw(x1, gd, 5+rex.w); // r1 = (gd>>5)
ADDx_REG_LSL(x3, wback, x1, 2+rex.w); //(&ed)+=r1*4; if(!rex.w && !rex.is32bits) {SXTWx(x1, x1);}
ADDz_REG_LSL(x3, wback, x1, 2+rex.w); //(&ed)+=r1*4;
LDxw(x1, x3, fixedaddress); LDxw(x1, x3, fixedaddress);
ed = x1; ed = x1;
wback = x3; wback = x3;
@ -1951,8 +1953,9 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else { } else {
SMREAD(); SMREAD();
addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, NULL, 0, 0); addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, NULL, 0, 0);
ASRx(x1, gd, 5+rex.w); // r1 = (gd>>5) ASRxw(x1, gd, 5+rex.w); // r1 = (gd>>5)
ADDx_REG_LSL(x3, wback, x1, 2+rex.w); //(&ed)+=r1*4; if(!rex.w && !rex.is32bits) {SXTWx(x1, x1);}
ADDz_REG_LSL(x3, wback, x1, 2+rex.w); //(&ed)+=r1*4;
LDxw(x1, x3, fixedaddress); LDxw(x1, x3, fixedaddress);
ed = x1; ed = x1;
wback = x3; wback = x3;
@ -2119,8 +2122,9 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else { } else {
SMREAD(); SMREAD();
addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, NULL, 0, 0); addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, NULL, 0, 0);
ASRx(x1, gd, 5+rex.w); // r1 = (gd>>5) ASRxw(x1, gd, 5+rex.w); // r1 = (gd>>5)
ADDx_REG_LSL(x3, wback, x1, 2+rex.w); //(&ed)+=r1*4; if(!rex.w && !rex.is32bits) {SXTWx(x1, x1);}
ADDz_REG_LSL(x3, wback, x1, 2+rex.w); //(&ed)+=r1*4;
LDxw(x1, x3, fixedaddress); LDxw(x1, x3, fixedaddress);
ed = x1; ed = x1;
wback = x3; wback = x3;