mirror of
https://github.com/ptitSeb/box64.git
synced 2024-11-28 01:01:03 +00:00
Added F2/F3 prefix handling and a bunch of F2 0F and F3 0F opcodes
This commit is contained in:
parent
5119464274
commit
7694594f8b
@ -113,6 +113,8 @@ set(ELFLOADER_SRC
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"${BOX64_ROOT}/src/emu/x64run66.c"
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"${BOX64_ROOT}/src/emu/x64rund9.c"
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"${BOX64_ROOT}/src/emu/x64rundb.c"
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"${BOX64_ROOT}/src/emu/x64runf20f.c"
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"${BOX64_ROOT}/src/emu/x64runf30f.c"
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"${BOX64_ROOT}/src/emu/x64run_private.c"
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"${BOX64_ROOT}/src/emu/x64syscall.c"
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"${BOX64_ROOT}/src/emu/x64tls.c"
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@ -19,12 +19,16 @@
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#define GETGB opgd=GetGb(emu, rex, nextop)
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#define GETEW oped=GetEw(emu, rex, nextop)
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#define GETGW opgd=GetGw(emu, rex, nextop)
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#define GETEX opex=GetEx(emu, rex, nextop)
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#define GETGX opgx=GetGx(emu, rex, nextop)
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#define ED oped
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#define GD opgd
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#define EB oped
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#define GB opgd->byte[0]
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#define EW oped
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#define GW opgd
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#define EX opex
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#define GX opgx
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#define GOCOND(BASE, PREFIX, CONDITIONAL) \
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case BASE+0x0: \
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@ -40,6 +40,7 @@ int Run(x64emu_t *emu, int step)
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uint64_t tmp64u;
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int32_t tmp32s;
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rex_t rex;
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int rep; // 0 none, 1=F2 prefix, 2=F3 prefix
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int unimp = 0;
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if(emu->quit)
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@ -62,6 +63,12 @@ x64emurun:
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emu->old_ip = R_RIP;
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opcode = F8;
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rep = 0;
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while((opcode==0xF2) || (opcode==0xF3)) {
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rep = opcode-0xF1;
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opcode = F8;
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}
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if(opcode>=0x40 && opcode<=0x4f) {
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rex.rex = opcode;
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opcode = F8;
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@ -114,9 +121,25 @@ x64emurun:
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GO(0x00, add) /* ADD 0x00 -> 0x05 */
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GO(0x08, or) /* OR 0x08 -> 0x0D */
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case 0x0F: /* More instructions */
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if(Run0F(emu, rex)) {
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unimp = 1;
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goto fini;
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switch(rep) {
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case 1:
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if(RunF20F(emu, rex)) {
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unimp = 1;
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goto fini;
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}
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break;
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case 2:
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if(RunF30F(emu, rex)) {
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unimp = 1;
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goto fini;
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}
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break;
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default:
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if(Run0F(emu, rex)) {
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unimp = 1;
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goto fini;
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}
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break;
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}
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if(emu->quit)
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goto fini;
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@ -231,6 +231,8 @@ int Run66(x64emu_t *emu, rex_t rex);
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//int Run67(x64emu_t *emu, rex_t rex);
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int RunD9(x64emu_t *emu, rex_t rex);
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int RunDB(x64emu_t *emu, rex_t rex);
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int RunF20F(x64emu_t *emu, rex_t rex);
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int RunF30F(x64emu_t *emu, rex_t rex);
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//void Run660F(x64emu_t *emu);
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//void Run66D9(x64emu_t *emu); // x87
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//void Run6766(x64emu_t *emu);
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63
src/emu/x64runf20f.c
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63
src/emu/x64runf20f.c
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@ -0,0 +1,63 @@
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#define _GNU_SOURCE
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <math.h>
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#include <string.h>
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#include <signal.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include "debug.h"
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#include "box64stack.h"
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#include "x64emu.h"
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#include "x64run.h"
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#include "x64emu_private.h"
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#include "x64run_private.h"
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#include "x64primop.h"
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#include "x64trace.h"
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#include "x87emu_private.h"
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#include "box64context.h"
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//#include "my_cpuid.h"
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#include "bridge.h"
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//#include "signals.h"
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#ifdef DYNAREC
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#include "../dynarec/arm_lock_helper.h"
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#endif
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#include "modrm.h"
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int RunF20F(x64emu_t *emu, rex_t rex)
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{
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uint8_t opcode;
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uint8_t nextop;
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int32_t tmp32s;
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reg64_t *oped, *opgd;
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sse_regs_t *opex, *opgx;
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opcode = F8;
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switch(opcode) {
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case 0x10: /* MOVSD Gx, Ex */
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nextop = F8;
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GETEX;
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GETGX;
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GX->q[0] = EX->q[0];
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if((nextop&0xC0)!=0xC0) {
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// EX is not a register
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GX->q[1] = 0;
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}
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break;
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case 0x11: /* MOVSD Ex, Gx */
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nextop = F8;
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GETEX;
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GETGX;
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EX->q[0] = GX->q[0];
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break;
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default:
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return 1;
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}
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return 0;
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}
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83
src/emu/x64runf30f.c
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83
src/emu/x64runf30f.c
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@ -0,0 +1,83 @@
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#define _GNU_SOURCE
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <math.h>
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#include <string.h>
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#include <signal.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include "debug.h"
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#include "box64stack.h"
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#include "x64emu.h"
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#include "x64run.h"
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#include "x64emu_private.h"
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#include "x64run_private.h"
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#include "x64primop.h"
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#include "x64trace.h"
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#include "x87emu_private.h"
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#include "box64context.h"
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//#include "my_cpuid.h"
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#include "bridge.h"
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//#include "signals.h"
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#ifdef DYNAREC
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#include "../dynarec/arm_lock_helper.h"
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#endif
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#include "modrm.h"
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int RunF30F(x64emu_t *emu, rex_t rex)
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{
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uint8_t opcode;
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uint8_t nextop;
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int32_t tmp32s;
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reg64_t *oped, *opgd;
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sse_regs_t *opex, *opgx;
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opcode = F8;
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switch(opcode) {
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case 0x10: /* MOVSS Gx Ex */
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nextop = F8;
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GETEX;
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GETGX;
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GX->ud[0] = EX->ud[0];
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if((nextop&0xC0)!=0xC0) {
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// EX is not a register (reg to reg only move 31:0)
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GX->ud[1] = GX->ud[2] = GX->ud[3] = 0;
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}
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break;
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case 0x11: /* MOVSS Ex Gx */
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nextop = F8;
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GETEX;
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GETGX;
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EX->ud[0] = GX->ud[0];
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break;
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case 0x2A: /* CVTSI2SS Gx, Ed */
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nextop = F8;
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GETED;
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GETGX;
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GX->f[0] = ED->sdword[0];
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break;
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case 0x59: /* MULSS Gx, Ex */
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nextop = F8;
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GETEX;
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GETGX;
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GX->f[0] *= EX->f[0];
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break;
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case 0x5A: /* CVTSS2SD Gx, Ex */
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nextop = F8;
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GETEX;
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GETGX;
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GX->d[0] = EX->f[0];
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break;
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default:
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return 1;
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}
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return 0;
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}
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