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[ARM64_DYNAREC] Re-enable weakbarrier for dmb.ishst (#2048)
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@ -169,9 +169,14 @@ Define Box64's Dynarec max allowed forward value when building Block.
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#### BOX64_DYNAREC_STRONGMEM *
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#### BOX64_DYNAREC_STRONGMEM *
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Enable/Disable simulation of Strong Memory model
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Enable/Disable simulation of Strong Memory model
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* 0 : Don't try anything special (Default.)
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* 0 : Don't try anything special (Default.)
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* 1 : Enable some Memory Barrier when writting to memory (on some MOV opcode) to simulate Strong Memory Model while trying to limit performance impact (Default when libmonobdwgc-2.0.so is loaded)
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* 1 : Enable some memory barriers when writting to memory to simulate the Strong Memory Model in a limited way (Default when libmonobdwgc-2.0.so is loaded)
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* 2 : All 1. plus a memory barrier on every write to memory using MOV
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* 2 : All 1. plus memory barriers on SIMD instructions
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* 3 : All 2. plus Memory Barrier when reading from memory and on some SSE/SSE2 opcodes too
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* 3 : All 2. plus more memory barriers on a regular basis
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#### BOX64_DYNAREC_WEAKBARRIER *
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Use weak memory barriers to reduce the performance impact by STRONGMEM
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* 0 : Use regular safe barrier (Default.)
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* 1 : Use weak barriers to have more performance boost
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#### BOX64_DYNAREC_X87DOUBLE *
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#### BOX64_DYNAREC_X87DOUBLE *
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Force the use of Double for x87 emulation
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Force the use of Double for x87 emulation
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@ -296,8 +296,16 @@ Define Box64's Dynarec max allowed forward value when building Block.
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Enable/Disable simulation of Strong Memory model
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Enable/Disable simulation of Strong Memory model
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* 0 : Don't try anything special (Default.)
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* 0 : Don't try anything special (Default.)
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* 1 : Enable some Memory Barrier when reading from memory (on some MOV opcode) to simulate Strong Memory Model while trying to limit performance impact (Default when libmonobdwgc-2.0.so is loaded)
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* 1 : Enable some memory barriers when writting to memory to simulate the Strong Memory Model in a limited way (Default when libmonobdwgc-2.0.so is loaded)
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* 2 : Enable some Memory Barrier when reading from memory (on some MOV opcode) to simulate Strong Memory Model
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* 2 : All 1. plus memory barriers on SIMD instructions
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* 3 : All 2. plus more memory barriers on a regular basis
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=item B<BOX64_DYNAREC_WEAKBARRIER>=I<0|1>
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Use weak memory barriers to reduce the performance impact by STRONGMEM
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* 0 : Use regular safe barrier (Default.)
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* 1 : Use weak barriers to have more performance boost
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=item B<BOX64_DYNAREC_X87DOUBLE>=I<0|1>
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=item B<BOX64_DYNAREC_X87DOUBLE>=I<0|1>
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@ -60,7 +60,7 @@
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*/
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*/
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#define STRONGMEM_SIMD_WRITE 2 // The level of SIMD memory writes will be tracked
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#define STRONGMEM_SIMD_WRITE 2 // The level of SIMD memory writes will be tracked
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#define STRONGMEM_LAST_WRITE 2 // The level of a barrier before the last guest memory store will be put
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#define STRONGMEM_LAST_WRITE 1 // The level of a barrier before the last guest memory store will be put
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#define STRONGMEM_SEQ_WRITE 3 // The level of a barrier at every third memory store will be put
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#define STRONGMEM_SEQ_WRITE 3 // The level of a barrier at every third memory store will be put
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#if STEP == 1
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#if STEP == 1
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@ -165,9 +165,15 @@
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do { \
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do { \
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if (box64_dynarec_strongmem >= dyn->insts[ninst].will_write && dyn->smwrite == 0) { \
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if (box64_dynarec_strongmem >= dyn->insts[ninst].will_write && dyn->smwrite == 0) { \
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/* Will write but never written, this is the start of a SEQ, put a barrier. */ \
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/* Will write but never written, this is the start of a SEQ, put a barrier. */ \
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if (box64_dynarec_weakbarrier) \
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DMB_ISHST(); \
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else \
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DMB_ISH(); \
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DMB_ISH(); \
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} else if (box64_dynarec_strongmem >= STRONGMEM_LAST_WRITE && dyn->insts[ninst].last_write) { \
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} else if (box64_dynarec_strongmem >= STRONGMEM_LAST_WRITE && dyn->insts[ninst].last_write) { \
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/* Last write, put a barrier */ \
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/* Last write, put a barrier */ \
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if (box64_dynarec_weakbarrier) \
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DMB_ISHST(); \
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else \
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DMB_ISH(); \
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DMB_ISH(); \
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} \
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} \
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} while (0)
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} while (0)
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@ -198,6 +204,9 @@
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--i; \
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--i; \
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if (i >= 0) { \
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if (i >= 0) { \
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/* It's a SEQ, put a barrier here. */ \
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/* It's a SEQ, put a barrier here. */ \
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if (box64_dynarec_weakbarrier) \
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DMB_ISHST(); \
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else \
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DMB_ISH(); \
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DMB_ISH(); \
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} \
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} \
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} \
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} \
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