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[ARM64_DYNAREC] More optimizations on strongmem emulation (#2051)
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Yang Liu
GitHub
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9757d1b67a
@ -169,15 +169,15 @@ Define Box64's Dynarec max allowed forward value when building Block.
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#### BOX64_DYNAREC_STRONGMEM *
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Enable/Disable simulation of Strong Memory model
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* 0 : Don't try anything special (Default.)
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* 1 : Enable some memory barriers when writting to memory to simulate the Strong Memory Model in a limited way (Default when libmonobdwgc-2.0.so is loaded)
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* 1 : Enable some memory barriers when writing to memory to simulate the Strong Memory Model in a limited way (Default when libmonobdwgc-2.0.so is loaded)
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* 2 : All 1. plus memory barriers on SIMD instructions
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* 3 : All 2. plus more memory barriers on a regular basis
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#### BOX64_DYNAREC_WEAKBARRIER *
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Use weak memory barriers to reduce the performance impact by STRONGMEM
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Tweaking the memory barriers to reduce the performance impact by STRONGMEM
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* 0 : Use regular safe barrier (Default.)
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* 1 : Use weak barriers to have more performance boost
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* 2 : Disable the last write barriers to have even more performance boost
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* 2 : All 1. Plus disabled the last write barriers
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#### BOX64_DYNAREC_X87DOUBLE *
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Force the use of Double for x87 emulation
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@ -296,17 +296,17 @@ Define Box64's Dynarec max allowed forward value when building Block.
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Enable/Disable simulation of Strong Memory model
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* 0 : Don't try anything special (Default.)
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* 1 : Enable some memory barriers when writting to memory to simulate the Strong Memory Model in a limited way (Default when libmonobdwgc-2.0.so is loaded)
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* 1 : Enable some memory barriers when writing to memory to simulate the Strong Memory Model in a limited way (Default when libmonobdwgc-2.0.so is loaded)
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* 2 : All 1. plus memory barriers on SIMD instructions
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* 3 : All 2. plus more memory barriers on a regular basis
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=item B<BOX64_DYNAREC_WEAKBARRIER>=I<0|1>
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Use weak memory barriers to reduce the performance impact by STRONGMEM
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Tweaking the memory barriers to reduce the performance impact by STRONGMEM
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* 0 : Use regular safe barrier (Default.)
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* 1 : Use weak barriers to have more performance boost
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* 2 : Disable the last write barriers to have even more performance boost
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* 2 : All 1. Plus disabled the last write barriers
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=item B<BOX64_DYNAREC_X87DOUBLE>=I<0|1>
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@ -53,10 +53,14 @@
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* - SIMD operations (c2)
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* 4. After every third guest memory store in a SEQ (d)
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*
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* STRONGMEM levels:
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* LEVEL1: Includes a1, b1
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* LEVEL2: Includes LEVEL1, plus a2, b2, c1, c2
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* LEVEL3: Includes LEVEL2, plus d
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* STRONGMEM levels (coarse-grained):
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* 1: Includes a1, b1, c1
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* 2: Includes LEVEL1, plus a2, b2, c2
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* 3: Includes LEVEL2, plus d
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*
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* WEAKBARRIER levels (fine-grained):
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* 1: Use dmb.ishld and dmb.ishst over dmb.ish for more performance
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* 2. All 1. Plus disabled the last write barriers (c1, c2)
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*/
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#define STRONGMEM_SIMD_WRITE 2 // The level of SIMD memory writes will be tracked
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@ -161,21 +165,22 @@
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} while (0)
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// An opcode will write memory, this will be put before the STORE instruction automatically.
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#define WILLWRITE() \
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do { \
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if (box64_dynarec_strongmem >= dyn->insts[ninst].will_write && dyn->smwrite == 0) { \
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/* Will write but never written, this is the start of a SEQ, put a barrier. */ \
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if (box64_dynarec_weakbarrier) \
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DMB_ISHST(); \
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else \
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DMB_ISH(); \
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} else if (box64_dynarec_strongmem >= STRONGMEM_LAST_WRITE && box64_dynarec_weakbarrier <= 1 && dyn->insts[ninst].last_write) { \
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/* Last write, put a barrier */ \
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if (box64_dynarec_weakbarrier) \
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DMB_ISHST(); \
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else \
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DMB_ISH(); \
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} \
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#define WILLWRITE() \
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do { \
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if (box64_dynarec_strongmem >= dyn->insts[ninst].will_write && dyn->smwrite == 0) { \
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/* Will write but never written, this is the start of a SEQ, put a barrier. */ \
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if (box64_dynarec_weakbarrier) \
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DMB_ISHLD(); \
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else \
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DMB_ISH(); \
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} else if (box64_dynarec_strongmem >= STRONGMEM_LAST_WRITE && box64_dynarec_weakbarrier != 2 \
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&& dyn->insts[ninst].last_write) { \
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/* Last write, put a barrier */ \
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if (box64_dynarec_weakbarrier) \
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DMB_ISHST(); \
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else \
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DMB_ISH(); \
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} \
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} while (0)
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// Similar to WILLWRITE, but checks lock.
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@ -195,22 +200,19 @@
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} while (0)
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// Will be put at the end of the SEQ
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#define SMEND() \
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do { \
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if (box64_dynarec_strongmem) { \
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/* Check if there is any guest memory write. */ \
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int i = ninst; \
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while (i >= 0 && !dyn->insts[i].will_write) \
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--i; \
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if (i >= 0) { \
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/* It's a SEQ, put a barrier here. */ \
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if (box64_dynarec_weakbarrier) \
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DMB_ISHST(); \
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else \
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DMB_ISH(); \
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} \
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} \
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dyn->smwrite = 0; \
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#define SMEND() \
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do { \
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if (box64_dynarec_strongmem) { \
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/* It's a SEQ, put a barrier here. */ \
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if (dyn->smwrite) { \
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/* Check if the next instruction has a end loop mark */ \
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if (box64_dynarec_weakbarrier) \
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DMB_ISHST(); \
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else \
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DMB_ISH(); \
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} \
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} \
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dyn->smwrite = 0; \
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} while (0)
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// The barrier.
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@ -1283,9 +1285,9 @@
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#define FTABLE64(A, V)
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#endif
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#define ARCH_INIT() \
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dyn->smread = dyn->smwrite = 0; \
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dyn->doublepush = 0; \
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#define ARCH_INIT() \
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SMSTART(); \
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dyn->doublepush = 0; \
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dyn->doublepop = 0;
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#define ARCH_RESET()
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@ -106,9 +106,9 @@ typedef struct instruction_arm64_s {
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uint16_t ymm0_out; // the ymm0 at th end of the opcode
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uint16_t ymm0_pass2, ymm0_pass3;
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uint8_t barrier_maybe;
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uint8_t will_write;
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uint8_t last_write;
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uint8_t lock;
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uint8_t will_write:2; // [strongmem] will write to memory
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uint8_t last_write:1; // [strongmem] the last write in a SEQ
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uint8_t lock:1; // [strongmem] lock semantic
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uint8_t set_nat_flags; // 0 or combinaison of native flags define
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uint8_t use_nat_flags; // 0 or combinaison of native flags define
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uint8_t use_nat_flags_before; // 0 or combinaison of native flags define
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@ -159,7 +159,6 @@ typedef struct dynarec_arm_s {
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int forward_ninst; // ninst at the forward point
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uint16_t ymm_zero; // bitmap of ymm to zero at purge
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uint8_t smwrite; // for strongmem model emulation
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uint8_t smread;
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uint8_t doublepush;
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uint8_t doublepop;
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uint8_t always_test;
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