From 99948b601b25ff830be84fca0c3da9d605abb061 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Sat, 8 Apr 2023 14:50:39 +0200 Subject: [PATCH] Added 66 0F 38 07 opcode ([ARM64_DYNAREC] too) --- src/dynarec/arm64/dynarec_arm64_660f.c | 22 +++++++++++++++++++++- src/emu/x64run660f.c | 18 +++++++++++++++++- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c index dadb78b3..c32c35e7 100755 --- a/src/dynarec/arm64/dynarec_arm64_660f.c +++ b/src/dynarec/arm64/dynarec_arm64_660f.c @@ -298,7 +298,27 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n } VADDPQ_32(q0, q0, v0); break; - + case 0x07: + INST_NAME("PHSUBSW Gx, Ex"); + nextop = F8; + GETGX(q0, 1); + GETEX(q1, 0, 0); + v0 = fpu_get_scratch(dyn); + VTRNQ2_16(v0, q0, q0); // v0 have all odd elements (in double) + NEGQ_16(v0, v0); + VTRNQ1_16(q0, q0, v0); // re-inject negged element to q0 + SADDLPQ_16(q0, q0); // there is no Add Pair with saturation... + SQXTN_16(q0, q0); + if(q0!=q1) { + VTRNQ2_16(v0, q1, q1); + NEGQ_16(v0, v0); + VTRNQ1_16(v0, q1, v0); + SADDLPQ_16(v0, v0); + SQXTN2_16(q0, v0); + } else { + VMOVeD(q0, 1, q0, 0); + } + break; case 0x08: INST_NAME("PSIGNB Gx, Ex"); nextop = F8; diff --git a/src/emu/x64run660f.c b/src/emu/x64run660f.c index a0f7f6ae..29f36fcd 100644 --- a/src/emu/x64run660f.c +++ b/src/emu/x64run660f.c @@ -357,7 +357,23 @@ uintptr_t Run660F(x64emu_t *emu, rex_t rex, uintptr_t addr) GX->sd[2+i] = EX->sd[i*2+0] - EX->sd[i*2+1]; } break; - + case 0x07: /* PHSUBSW Gx, Ex */ + nextop = F8; + GETEX(0); + GETGX; + for (int i=0; i<4; ++i) { + tmp32s = GX->sw[i*2+0] - GX->sw[i*2+1]; + GX->sw[i] = (tmp32s<-32768)?-32768:((tmp32s>32767)?32767:tmp32s); + } + if(GX == EX) { + GX->q[1] = GX->q[0]; + } else { + for (int i=0; i<4; ++i) { + tmp32s = EX->sw[i*2+0] - EX->sw[i*2+1]; + GX->sw[4+i] = (tmp32s<-32768)?-32768:((tmp32s>32767)?32767:tmp32s); + } + } + break; case 0x08: /* PSIGNB Gx, Ex */ nextop = F8; GETEX(0);