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https://github.com/ptitSeb/box64.git
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[ARM64_DYNAREC] Improved some specific cases of pcmpestri opcode
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ptitSeb
parent
8c19c3a72c
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b6f58caf24
@ -1564,6 +1564,15 @@ int convert_bitmask(uint64_t bitmask);
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// Signed saturating extract Unsigned Narrow, takes Rn element and reduce 16->8 with Unsigned saturation and fit higher part of Rd
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#define SQXTUN2_8(Rd, Rn) EMIT(QXTUN_vector(1, 1, 0b00, Rn, Rd))
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#define XTN_vector(Q, size, Rn, Rd) ((Q)<<30 | 0b01110<<24 | (size)<<22 | 0b10000<<17 | 0b10010<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
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// Xtract narrow to X bits
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#define XTN_8(Vd, Vn) EMIT(XTN_vector(0, 0b00, Vn, Vd))
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#define XTN_16(Vd, Vn) EMIT(XTN_vector(0, 0b01, Vn, Vd))
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#define XTN_32(Vd, Vn) EMIT(XTN_vector(0, 0b10, Vn, Vd))
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#define XTN2_8(Vd, Vn) EMIT(XTN_vector(1, 0b00, Vn, Vd))
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#define XTN2_16(Vd, Vn) EMIT(XTN_vector(1, 0b01, Vn, Vd))
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#define XTN2_32(Vd, Vn) EMIT(XTN_vector(1, 0b10, Vn, Vd))
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// Integer CMP
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// EQual
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#define CMEQ_vector(Q, U, size, Rm, Rn, Rd) ((Q)<<30 | (U)<<29 | 0b01110<<24 | (size)<<22 | 1<<21 | (Rm)<<16 | 0b10001<<11 | 1<<10 | (Rn)<<5 | (Rd))
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@ -1236,7 +1236,8 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
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ADDx_U12(x3, xEmu, offsetof(x64emu_t, xmm[gd]));
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if(MODREG) {
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ed = (nextop&7)+(rex.b<<3);
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sse_reflect_reg(dyn, ninst, ed);
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if(ed>7)
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sse_reflect_reg(dyn, ninst, ed);
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ADDx_U12(x1, xEmu, offsetof(x64emu_t, xmm[ed]));
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} else {
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addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 1);
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@ -1286,33 +1287,147 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
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SETFLAGS(X_ALL, SF_SET);
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nextop = F8;
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GETG;
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sse_reflect_reg(dyn, ninst, gd);
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ADDx_U12(x3, xEmu, offsetof(x64emu_t, xmm[gd]));
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if(MODREG) {
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ed = (nextop&7)+(rex.b<<3);
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sse_reflect_reg(dyn, ninst, ed);
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ADDx_U12(x1, xEmu, offsetof(x64emu_t, xmm[ed]));
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} else {
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addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 1);
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if(ed!=x1) {
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MOVx_REG(x1, ed);
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u8 = geted_ib(dyn, addr, ninst, nextop);
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if((u8&0b1100)==0b1000) {
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// this case is (un)signed word, equal each
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GETGX(v0, 0);
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GETEX(v1, 0, 1);
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u8 = F8;
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q0 = fpu_get_scratch(dyn);
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if(u8&1) {
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//16bits
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VCMEQQ_16(q0, v0, v1); // equal => mask regs
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XTN_8(q0, q0); // 8 bits mask, in lower 64bits
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// transform that a mask in x1
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q1 = fpu_get_scratch(dyn);
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VSHL_8(q0, q0, 7); // keep only bit 0x80
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TABLE64(x1, (uintptr_t)&mask_shift8);
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VLDR64_U12(q1, x1, 0); // load shift
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USHL_8(q0, q0, q1); // shift
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UADDLV_8(q0, q0); // accumulate
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VMOVBto(x1, q0, 0);
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} else {
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//8 bits
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VCMEQQ_8(q0, v0, v1); // equal => mask regs
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// transform that a mask in x1
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q1 = fpu_get_scratch(dyn);
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d0 = fpu_get_scratch(dyn);
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VSHL_8(d0, q0, 7); // keep only bit 0x80
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TABLE64(x1, (uintptr_t)&mask_shift8);
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VLDR64_U12(q1, x1, 0); // load shift
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USHL_8(d0, d0, q1); // shift
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UADDLV_8(d0, d0); // accumulate
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VMOVBto(x1, d0, 0);
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// high part
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VMOVeD(d0, 0, q0, 1);
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VSHL_8(d0, d0, 7); // keep only bit 0x80
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USHL_8(d0, d0, q1); // shift
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UADDLV_8(d0, d0); // accumulate
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VMOVBto(x2, d0, 0);
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BFIw(x1, x2, 8, 8); // insert
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}
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// get abs of eax / edx and find min
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ADDSxw_U12(x2, xRAX, 0);
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Bcond(cPL, 4+4);
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NEGxw_REG(x2, x2);
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ADDSxw_U12(x3, xRDX, 0);
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Bcond(cPL, 4+4);
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NEGxw_REG(x3, x3);
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MOV32w(x4, (u8&1)?8:16);
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CMPSw_REG(x3, x4);
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CSELw(x3, x3, x4, cLT); // x3 is lmem
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CMPSw_REG(x2, x4);
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CSELw(x2, x2, x4, cLT); // x2 is lreg
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CMPSw_REG(x2, x3);
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CSELw(x5, x3, x2, cLT); // x5 is max(lmem, lreg)
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CSELw(x2, x2, x3, cLT); // x2 is min(lmem, lreg)
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// x2 is min length 0-n_packed
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MVNw_REG(x4, xZR);
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LSLw_REG(x7, x4, x2);
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BICw_REG(x1, x1, x7);
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LSLw_REG(x4, x4, x5);
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ORRw_REG(x1, x1, x4);
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ANDw_mask(x1, x1, 0, (u8&1)?7:15);
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// x1 is intres1, transform to intres2
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switch((u8>>4)&3) {
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case 0b01:
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MOV32w(x4, (1<<((u8&1)?8:16))-1);
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EORw_REG(x1, x1, x4);
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break;
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case 0b11:
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MOV32w(x4, 1);
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LSLw_REG(x4, x4, x3);
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SUBw_U12(x4, x4, 1);
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EORw_REG(x1, x1, x4);
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}
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// flags
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IFX(X_ALL) {
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SET_DFNONE(x4);
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IFX(X_CF) {
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CMPSw_REG(x1, xZR);
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CSETw(x4, cNE);
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BFIw(xFlags, x4, F_CF, 1);
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}
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IFX(X_ZF|X_SF) {
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MOV32w(x4, 8);
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IFX(X_ZF) {
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CMPSw_REG(x3, x4);
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CSETw(x4, cLT);
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BFIw(xFlags, x4, F_ZF, 1);
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}
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IFX(F_SF) {
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CMPSw_REG(x2, x4);
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CSETw(x4, cLT);
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BFIw(xFlags, x4, F_SF, 1);
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}
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}
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IFX(X_OF) {
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BFIw(xFlags, x1, F_OF, 1);
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}
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IFX(X_AF) {
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CMPSw_U12(x1, 0);
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CSETw(x4, cEQ);
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CMPSw_U12(x3, (u8&1)?8:16);
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CSETw(x5, cEQ);
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ANDw_REG(x4, x4, x5);
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BFIw(xFlags, x4, F_AF, 1);
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}
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IFX(X_PF) {
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BFCw(xFlags, F_PF, 1);
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}
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}
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} else {
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if(gd>7) // no need to reflect cache as xmm0-xmm7 will be saved before the function call anyway
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sse_reflect_reg(dyn, ninst, gd);
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ADDx_U12(x3, xEmu, offsetof(x64emu_t, xmm[gd]));
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if(MODREG) {
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ed = (nextop&7)+(rex.b<<3);
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if(ed>7)
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sse_reflect_reg(dyn, ninst, ed);
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ADDx_U12(x1, xEmu, offsetof(x64emu_t, xmm[ed]));
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} else {
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addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 1);
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if(ed!=x1) {
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MOVx_REG(x1, ed);
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}
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}
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MOVw_REG(x2, xRDX);
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MOVw_REG(x4, xRAX);
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u8 = F8;
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MOV32w(x5, u8);
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CALL(sse42_compare_string_explicit_len, x1);
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}
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MOVx_REG(x2, xRDX);
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MOVx_REG(x4, xRAX);
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u8 = F8;
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MOV32w(x5, u8);
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CALL(sse42_compare_string_explicit_len, x1);
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CBNZw_MARK(x1);
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MOV32w(xRCX, (u8&1)?8:16);
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B_NEXT_nocond;
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MARK;
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if(u8&0b1000000) {
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CBNZw_MARK(x1);
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MOV32w(xRCX, (u8&1)?8:16);
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B_NEXT_nocond;
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MARK;
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CLZw(xRCX, x1);
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MOV32w(x2, 31);
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SUBw_REG(xRCX, x2, xRCX);
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} else {
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RBITxw(xRCX, x1);
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ORRw_mask(xRCX, x1, (u8&1)?0b011000:0b010000,0);
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RBITw(xRCX, xRCX);
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CLZw(xRCX, xRCX);
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}
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break;
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@ -1325,7 +1440,8 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
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ADDx_U12(x2, xEmu, offsetof(x64emu_t, xmm[gd]));
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if(MODREG) {
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ed = (nextop&7)+(rex.b<<3);
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sse_reflect_reg(dyn, ninst, ed);
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if(ed>7)
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sse_reflect_reg(dyn, ninst, ed);
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ADDx_U12(x1, xEmu, offsetof(x64emu_t, xmm[ed]));
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} else {
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addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 1);
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@ -1373,11 +1489,13 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
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SETFLAGS(X_OF|X_CF|X_AF|X_ZF|X_SF|X_PF, SF_SET);
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nextop = F8;
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GETG;
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sse_reflect_reg(dyn, ninst, gd);
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if(gd>7)
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sse_reflect_reg(dyn, ninst, gd);
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ADDx_U12(x2, xEmu, offsetof(x64emu_t, xmm[gd]));
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if(MODREG) {
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ed = (nextop&7)+(rex.b<<3);
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sse_reflect_reg(dyn, ninst, ed);
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if(ed>7)
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sse_reflect_reg(dyn, ninst, ed);
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ADDx_U12(x1, xEmu, offsetof(x64emu_t, xmm[ed]));
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} else {
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addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 1);
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@ -24,6 +24,8 @@
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#define SF_SUB 4
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#define SF_SUBSET (SF_SUB|SF_SET)
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#define SF_SUBSET_PENDING (SF_SUBSET|SF_PENDING)
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#define SF_DF 8
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#define SF_SET_DF (SF_SET|SF_DF)
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typedef struct instruction_x64_s {
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uintptr_t addr; //address of the instruction
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