mirror of
https://github.com/ptitSeb/box64.git
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[ARM64_DYNAREC] Some refactor on 8/16/32/64bits SHL/SHR/SAR opcodes
This commit is contained in:
ptitSeb
parent
c87796e51c
commit
cd2638d11a
@ -1244,6 +1244,8 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
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case 6:
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INST_NAME("SHL Ed, CL");
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SETFLAGS(X_ALL, SF_SET_PENDING); // some flags are left undefined
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if(box64_dynarec_safeflags>1)
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MAYSETFLAGS();
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if(rex.w) {
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ANDx_mask(x3, xRCX, 1, 0, 0b00101); //mask=0x000000000000003f
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} else {
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@ -1258,6 +1260,8 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
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case 5:
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INST_NAME("SHR Ed, CL");
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SETFLAGS(X_ALL, SF_SET_PENDING); // some flags are left undefined
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if(box64_dynarec_safeflags>1)
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MAYSETFLAGS();
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if(rex.w) {
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ANDx_mask(x3, xRCX, 1, 0, 0b00101); //mask=0x000000000000003f
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} else {
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@ -1272,6 +1276,8 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
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case 7:
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INST_NAME("SAR Ed, CL");
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SETFLAGS(X_ALL, SF_SET_PENDING);
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if(box64_dynarec_safeflags>1)
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MAYSETFLAGS();
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if(rex.w) {
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ANDx_mask(x3, xRCX, 1, 0, 0b00101); //mask=0x000000000000003f
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} else {
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@ -1248,11 +1248,13 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
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case 4:
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case 6:
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INST_NAME("SHL Ed, Ib");
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SETFLAGS(X_ALL, SF_SET_PENDING); // some flags are left undefined
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GETED32(1);
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u8 = (F8)&(rex.w?0x3f:0x1f);
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emit_shl32c(dyn, ninst, rex, ed, u8, x3, x4);
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WBACK;
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if(u8) { //should create the geted32_ib utility function for that
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SETFLAGS(X_ALL, SF_SET_PENDING); // some flags are left undefined
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emit_shl32c(dyn, ninst, rex, ed, u8, x3, x4);
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WBACK;
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}
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break;
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case 5:
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INST_NAME("SHR Ed, Ib");
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@ -21,7 +21,7 @@
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#include "dynarec_arm64_functions.h"
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#include "dynarec_arm64_helper.h"
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// emit SHL32 instruction, from s1 , shift s2, store result in s1 using s3 and s4 as scratch. s3 can be same as s2
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// emit SHL32 instruction, from s1 , shift s2, store result in s1 using s3 and s4 as scratch. s3 can be same as s2. s2 must be non-0
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void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
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{
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MAYUSE(s2);
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@ -35,15 +35,6 @@ void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
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} else IFX(X_ALL) {
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SET_DFNONE(s4);
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}
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IFX(X_OF) {
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CMPSxw_U12(s2, 0);
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Bcond(cNE, +8+((dyn->insts[ninst].x64.gen_flags&X_PEND)?4:0));
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BFCw(xFlags, F_OF, 1);
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IFX(X_PEND) {
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STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
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}
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B_NEXT(cEQ);
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}
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IFX(X_CF | X_OF) {
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MOV32w(s4, rex.w?64:32);
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SUBxw_REG(s4, s4, s2);
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@ -54,29 +45,29 @@ void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
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IFX(X_PEND) {
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STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
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}
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IFX(X_OF) {
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CMPSxw_U12(s2, 1); // if s2==1
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LSRxw(s4, s1, (rex.w)?63:31);
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EORxw_REG(s3, s4, xFlags); // CF is set if OF is asked
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CSELw(s3, s3, wZR, cEQ);
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BFIw(xFlags, s3, F_OF, 1);
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}
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int need_tst = 0;
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IFX(X_ZF) need_tst = 1;
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IFXNATIVE(X_SF, NF_SF) need_tst = 1;
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if(need_tst) TSTxw_REG(s1, s1);
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IFX(X_SF) {
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IFNATIVE(NF_SF) {} else {
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IFX(X_OF) {} else {LSRxw(s4, s1, (rex.w)?63:31);}
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BFIw(xFlags, s4, F_SF, 1);
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}
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}
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IFX(X_ZF) {
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IFNATIVE(NF_EQ) {} else {
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CSETw(s4, cEQ);
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BFIw(xFlags, s4, F_ZF, 1);
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}
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}
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IFX(X_SF) {
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IFNATIVE(NF_SF) {} else {
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LSRxw(s4, s1, (rex.w)?63:31);
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BFIw(xFlags, s4, F_SF, 1);
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}
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}
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IFX(X_OF) {
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CMPSxw_U12(s2, 1); // if s2==1
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IFX(X_SF) {} else {LSRxw(s4, s1, (rex.w)?63:31);}
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EORxw_REG(s4, s4, xFlags); // CF is set if OF is asked
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CSELw(s4, s4, wZR, cEQ);
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BFIw(xFlags, s4, F_OF, 1);
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}
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if(box64_dynarec_test)
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IFX(X_AF) {
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BFCw(xFlags, F_AF, 1);
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@ -99,15 +90,6 @@ void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, i
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} else IFX(X_ALL) {
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SET_DFNONE(s4);
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}
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if(c==0) {
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IFX(X_OF) {
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BFCw(xFlags, F_OF, 1);
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}
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IFX(X_PEND) {
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STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
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}
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return;
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}
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IFX(X_CF|X_OF) {
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LSRxw(s3, s1, (rex.w?64:32)-c);
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BFIxw(xFlags, s3, F_CF, 1);
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@ -391,14 +373,14 @@ void emit_shl8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
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IFX(X_PEND) {
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STRB_U12(s1, xEmu, offsetof(x64emu_t, res));
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}
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COMP_ZFSF(s1, 8)
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IFX(X_OF) {
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CMPSw_U12(s2, 1); // if s2==1
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IFX2(X_SF, && !arm64_flagm) {} else {LSRw(s3, s1, 7);}
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LSRw(s3, s1, 7);
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EORw_REG(s4, s3, xFlags); // CF is set if OF is asked
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CSELw(s4, s4, wZR, cEQ);
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BFIw(xFlags, s4, F_OF, 1);
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}
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COMP_ZFSF(s1, 8)
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if(box64_dynarec_test)
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IFX(X_AF) {
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BFCw(xFlags, F_AF, 1);
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@ -433,7 +415,7 @@ void emit_shl8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
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COMP_ZFSF(s1, 8)
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IFX(X_OF) {
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if(c==1) {
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IFX2(X_SF, && !arm64_flagm) {} else {LSRw(s3, s1, 7);}
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IFX2(X_SF, && !arm64_flagm) {} else {LSRw(s3, s1, 7);} //use COMP_ZFSF operation
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EORw_REG(s4, s3, xFlags); // CF is set if OF is asked
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BFIw(xFlags, s4, F_OF, 1);
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} else {
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@ -447,11 +429,7 @@ void emit_shl8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
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emit_pf(dyn, ninst, s1, s4);
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}
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} else {
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IFX(X_CF) {
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LSLw(s3, s1, c-1);
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BFXILw(xFlags, s3, 7, 1); // insert F_CF from s3[7:1]
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}
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IFXNATIVE(X_ZF|X_SF, NF_EQ|NF_SF) {
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IFXNATIVE(X_ZF|X_SF|X_CF, NF_EQ|NF_SF|NF_CF) {
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SUBSw_REG(s1, s1, s1);
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} else {
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MOVw_REG(s1, xZR);
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@ -459,6 +437,10 @@ void emit_shl8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
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IFX(X_PEND) {
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STRB_U12(s1, xEmu, offsetof(x64emu_t, res));
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}
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IFX(X_CF) {
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// sub X, X will generate a carry flags
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IFNATIVE(NF_CF) {GEN_INVERTED_CARRY();} else {BFCw(xFlags, F_CF, 1);}
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}
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IFX(X_OF) {
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BFCw(xFlags, F_OF, 1);
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}
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@ -468,17 +450,14 @@ void emit_shl8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
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if(box64_dynarec_test) IFX(X_AF) {
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BFCw(xFlags, F_AF, 1);
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}
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IFX(X_PF | X_ZF) {
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IFNATIVE(NF_EQ) {IFX(X_PF) {MOV32w(s3, 1);}} else {
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MOV32w(s3, 1);
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IFX(X_ZF) {
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BFIw(xFlags, s3, F_ZF, 1);
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}
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}
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IFX(X_PF) {
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BFIw(xFlags, s3, F_PF, 1);
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IFX(X_ZF) {
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IFNATIVE(NF_EQ) {} else {
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ORRw_mask(xFlags, xFlags, 26, 0); //1<<F_ZF
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}
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}
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IFX(X_PF) {
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ORRw_mask(xFlags, xFlags, 30, 0); //1<<F_PF
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}
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}
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}
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@ -625,13 +604,18 @@ void emit_sar8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
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emit_pf(dyn, ninst, s1, s4);
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}
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} else {
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LSRw(s3, s1, 7);
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BFIw(xFlags, s3, F_CF, 1);
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BFIw(wFlags, s3, F_SF, 1);
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EORw_mask(s3, s3, 0, 0); //1
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BFIw(xFlags, s3, F_ZF, 1);
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MOV32w(s3, 1);
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BFIw(xFlags, s3, F_PF, 1);
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IFX(X_CF|X_ZF|X_SF|X_PF) {
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LSRw(s3, s1, 7);
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IFX(X_CF){ BFIw(xFlags, s3, F_CF, 1); }
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IFX(X_SF){ BFIw(wFlags, s3, F_SF, 1); }
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IFX(X_ZF) {
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EORw_mask(s3, s3, 0, 0); //1
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BFIw(xFlags, s3, F_ZF, 1);
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}
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IFX(X_PF) {
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ORRw_mask(xFlags, xFlags, 30, 0); //1<<F_PF
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}
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}
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}
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if(box64_dynarec_test)
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IFX(X_AF) {
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@ -659,14 +643,14 @@ void emit_shl16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
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IFX(X_PEND) {
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STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
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}
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COMP_ZFSF(s1, 16)
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IFX(X_OF) {
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CMPSw_U12(s2, 1); // if s2==1
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IFX2(X_SF, && !arm64_flagm) {} else {LSRw(s3, s1, 15);}
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LSRw(s3, s1, 15);
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EORw_REG(s4, s3, xFlags); // CF is set if OF is asked
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CSELw(s4, s4, wZR, cEQ);
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BFIw(xFlags, s4, F_OF, 1);
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}
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COMP_ZFSF(s1, 16)
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if(box64_dynarec_test)
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IFX(X_AF) {
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BFCw(xFlags, F_AF, 1);
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@ -701,7 +685,7 @@ void emit_shl16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
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COMP_ZFSF(s1, 16)
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IFX(X_OF) {
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if(c==1) {
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IFX2(X_SF, && !arm64_flagm) {} else {LSRw(s3, s1, 15);}
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IFX2(X_SF, && !arm64_flagm) {} else {LSRw(s3, s1, 15);} // use COMP_ZFSF operation
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EORw_REG(s4, s3, xFlags); // CF is set if OF is asked
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BFIw(xFlags, s4, F_OF, 1);
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} else {
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@ -714,17 +698,12 @@ void emit_shl16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
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IFX(X_PF) {
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if(c>7) {
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// the 0xff area will be 0, so PF is known
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MOV32w(s3, 1);
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BFIw(xFlags, s3, F_PF, 1);
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ORRw_mask(xFlags, xFlags, 30, 0); //1<<F_PF
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} else
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emit_pf(dyn, ninst, s1, s4);
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}
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} else {
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IFX(X_CF) {
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LSLw(s3, s1, c-1);
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BFXILw(xFlags, s3, 15, 1); // insert F_CF from s3[15:1]
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}
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IFXNATIVE(X_ZF|X_SF, NF_EQ|NF_SF) {
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IFXNATIVE(X_ZF|X_SF|X_CF, NF_EQ|NF_SF|NF_CF) {
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SUBSw_REG(s1, s1, s1);
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} else {
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MOVw_REG(s1, xZR);
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@ -735,23 +714,24 @@ void emit_shl16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
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IFX(X_OF) {
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BFCw(xFlags, F_OF, 1);
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}
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IFX(X_CF) {
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// sub X, X will generate a carry flags
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IFNATIVE(NF_CF) {GEN_INVERTED_CARRY();} else {BFCw(xFlags, F_CF, 1);}
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}
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IFX(X_SF) {
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IFNATIVE(NF_SF) {} else BFCw(xFlags, F_SF, 1);
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}
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if(box64_dynarec_test) IFX(X_AF) {
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BFCw(xFlags, F_AF, 1);
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}
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IFX(X_PF | X_ZF) {
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IFNATIVE(NF_EQ) {IFX(X_PF) {MOV32w(s3, 1);}} else {
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MOV32w(s3, 1);
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IFX(X_ZF) {
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BFIw(xFlags, s3, F_ZF, 1);
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}
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}
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IFX(X_PF) {
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BFIw(xFlags, s3, F_PF, 1);
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IFX(X_ZF) {
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IFNATIVE(NF_EQ) {} else {
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ORRw_mask(xFlags, xFlags, 26, 0); //1<<F_ZF
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}
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}
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IFX(X_PF) {
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ORRw_mask(xFlags, xFlags, 30, 0); //1<<F_PF
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}
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}
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}
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@ -850,12 +830,12 @@ void emit_sar16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
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IFX(X_PEND) {
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STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
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}
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COMP_ZFSF(s1, 16)
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IFX(X_OF) {
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SUBw_U12(s4, s2, 1);
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CBNZw(s4, 4+4);
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BFCw(xFlags, F_OF, 1);
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}
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COMP_ZFSF(s1, 16)
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if(box64_dynarec_test)
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IFX(X_AF) {
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BFCw(xFlags, F_AF, 1);
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