[RV64_DYNAREC] Added more opcodes for vector (#1992)

2024-11-23 06:30:22 +00:00 · 2024-11-02 02:36:23 +08:00 · 2024-11-02 02:36:23 +08:00 · cf9f8d0535
commit cf9f8d0535
parent 9e43737e18
2 changed files with 39 additions and 0 deletions
--- a/src/dynarec/rv64/dynarec_rv64_660f_vector.c
+++ b/src/dynarec/rv64/dynarec_rv64_660f_vector.c
@ -850,6 +850,7 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
                    VECTOR_LOAD_VMASK((u8 & 0xf), x4, 1);
                    VMERGE_VVM(q0, v1, d0);
                    break;
+                case 0x63: return 0;
                default: DEFAULT_VECTOR;
            }
            break;
--- a/src/dynarec/rv64/dynarec_rv64_f30f_vector.c
+++ b/src/dynarec/rv64/dynarec_rv64_f30f_vector.c
@ -96,6 +96,44 @@ uintptr_t dynarec64_F30F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
                SMWRITE2();
            }
            break;
+        case 0x12:
+            INST_NAME("MOVSLDUP Gx, Ex");
+            nextop = F8;
+            SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1);
+            if (MODREG) {
+                q1 = sse_get_reg_vector(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), 0, VECTOR_SEW64);
+            } else {
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, x2, &fixedaddress, rex, NULL, 0, 0);
+                q1 = fpu_get_scratch(dyn);
+                VLE32_V(q1, ed, VECTOR_UNMASKED, VECTOR_NFIELD1);
+            }
+            GETGX_empty_vector(q0);
+            ADDI(x4, xZR, 32);
+            v0 = fpu_get_scratch(dyn);
+            VSLL_VX(q0, q1, x4, VECTOR_UNMASKED);
+            VSRL_VX(v0, q0, x4, VECTOR_UNMASKED);
+            VOR_VV(q0, q0, v0, VECTOR_UNMASKED);
+            break;
+        case 0x16:
+            INST_NAME("MOVSHDUP Gx, Ex");
+            nextop = F8;
+            SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1);
+            if (MODREG) {
+                q1 = sse_get_reg_vector(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), 0, VECTOR_SEW64);
+            } else {
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, x2, &fixedaddress, rex, NULL, 0, 0);
+                q1 = fpu_get_scratch(dyn);
+                VLE32_V(q1, ed, VECTOR_UNMASKED, VECTOR_NFIELD1);
+            }
+            GETGX_empty_vector(q0);
+            ADDI(x4, xZR, 32);
+            v0 = fpu_get_scratch(dyn);
+            VSRL_VX(q0, q1, x4, VECTOR_UNMASKED);
+            VSLL_VX(v0, q0, x4, VECTOR_UNMASKED);
+            VOR_VV(q0, q0, v0, VECTOR_UNMASKED);
+            break;
        case 0x1E:
            return 0;
        case 0x2A: