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[RV64_DYNAREC] Added more opcodes for Stardew Valley (#666)
* [RV64_DYNAREC] Added 66 0F 70 PSHUFD opcode * [RV64_DYNAREC] Added F2 0F 5E DIVSD opcode * [RV64_DYNAREC] Added F2 0F 2A CVTSI2SD opcode
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@ -161,6 +161,22 @@ uintptr_t dynarec64_660F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
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SD(x3, gback, 0);
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SD(x4, gback, 8);
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break;
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case 0x70: // TODO: Optimize this!
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INST_NAME("PSHUFD Gx,Ex,Ib");
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nextop = F8;
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GETGX(x1);
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GETEX(x2, 1);
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u8 = F8;
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i32 = -1;
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for (int i=0; i<4; ++i) {
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int32_t idx = (u8>>(i*2))&3;
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if (idx!=i32) {
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LWU(x4, wback, fixedaddress+idx*4);
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i32 = idx;
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}
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SW(x4, gback, i*4);
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}
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break;
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case 0x72:
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nextop = F8;
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switch((nextop>>3)&7) {
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@ -179,7 +179,7 @@ uintptr_t dynarec64_DB(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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v1 = x87_do_push(dyn, ninst, x1, EXT_CACHE_ST_D);
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addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
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LW(x1, ed, fixedaddress);
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FCVTDW(v1, x1); // i32 -> double
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FCVTDW(v1, x1, RD_RNE); // i32 -> double
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break;
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case 1:
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INST_NAME("FISTTP Ed, ST0");
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@ -79,7 +79,17 @@ uintptr_t dynarec64_F20F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
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SMWRITE2();
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}
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break;
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case 0x2A:
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INST_NAME("CVTSI2SD Gx, Ed");
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nextop = F8;
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GETGXSD(v0);
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GETED(0);
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if(rex.w) {
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FCVTDL(v0, ed, RD_RNE);
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} else {
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FCVTDW(v0, ed, RD_RNE);
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}
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break;
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case 0x38: // these are some more SSSE4.2+ opcodes
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opcode = F8;
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switch(opcode) {
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@ -124,7 +134,24 @@ uintptr_t dynarec64_F20F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
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GETEXSD(v1, 0);
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FSUBD(v0, v0, v1);
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break;
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case 0x5E:
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INST_NAME("DIVSD Gx, Ex");
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nextop = F8;
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GETGXSD(v0);
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GETEXSD(v1, 0);
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if(!box64_dynarec_fastnan) {
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FEQD(x3, v0, v0);
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FEQD(x4, v1, v1);
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}
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FDIVD(v0, v0, v1);
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if(!box64_dynarec_fastnan) {
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AND(x3, x3, x4);
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CBZ_NEXT(x3);
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FEQD(x3, v0, v0);
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CBNZ_NEXT(x3);
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FNEGD(v0, v0);
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}
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break;
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case 0xC2:
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INST_NAME("CMPSD Gx, Ex, Ib");
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nextop = F8;
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@ -469,7 +469,7 @@ f28–31 ft8–11 FP temporaries Caller
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// |rs1| => rd
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#define FABSD(rd, rs1) FSGNJXD(rd, rs1, rs1)
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// Convert from signed 32bits to Double
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#define FCVTDW(frd, rs1) EMIT(R_type(0b1101001, 0b00000, rs1, 0b000, frd, 0b1010011))
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#define FCVTDW(frd, rs1, rm) EMIT(R_type(0b1101001, 0b00000, rs1, rm, frd, 0b1010011))
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#define FEQD(rd, frs1, frs2) EMIT(R_type(0b1010001, frs2, frs1, 0b010, rd, 0b1010011))
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#define FLTD(rd, frs1, frs2) EMIT(R_type(0b1010001, frs2, frs1, 0b001, rd, 0b1010011))
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