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Fixed 32bits BE opcode to clear upper part of reg
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@ -364,7 +364,7 @@ x64emurun:
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if(rex.w)
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emu->regs[(opcode&7)+(rex.b<<3)].q[0] = F64;
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else
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emu->regs[(opcode&7)+(rex.b<<3)].dword[0] = F32;
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emu->regs[(opcode&7)+(rex.b<<3)].q[0] = F32;
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break;
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case 0xC1: /* GRP2 Ed,Ib */
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