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[DYNAREC] Added DMB emitter
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@ -555,6 +555,10 @@ Op is 20-27
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// Preload Cache Rn-Rm
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#define PLDn(Rn, Rm) EMIT(PLD_gen(0, 1, Rn, 0, 0, Rm))
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#define DMB_gen(opt) (0b1111<<28 | 0b01010111<<20 | 0b1111<<16 | 0b1111<<12 | 0b0000<<8 | 0b0101<<4 | (opt))
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// Data memory barrier Inner Sharable
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#define DMB_ISH() EMIT(DMB_gen(0b1011))
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#define SWP_gen(cond, B, Rn, Rt, Rt2) (cond | 0b0001<<24 | (B)<<22 | (Rn)<<16 | (Rt)<<12 | 0b1001<<4 | (Rt2))
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// SWAP (atomic) [Rn]->Rt2 / Rt->[Rn], Rt can be same as Rt2
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#define SWP(Rt, Rt2, Rn) EMIT(SWP_gen(c__, 0, Rn, Rt, Rt2))
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