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We can simplify component simulation through more streamlined structures

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This commit is contained in:
Gabriel Correia 2023-09-22 10:48:30 -07:00
parent d9c530858f
commit 9892174675
7 changed files with 19 additions and 86 deletions
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1
.idea/inspectionProfiles/Project_Default.xml
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@ -1,6 +1,7 @@
<component name="InspectionProjectProfileManager">
<profile version="1.0">
<option name="myName" value="Project Default" />
<inspection_tool class="ClangTidy" enabled="true" level="INFORMATION" enabled_by_default="true" />
<inspection_tool class="ConstantFunctionResult" enabled="false" level="WARNING" enabled_by_default="false" />
<inspection_tool class="OCUnusedGlobalDeclaration" enabled="false" level="WARNING" enabled_by_default="false" />
<inspection_tool class="UnusedParameter" enabled="false" level="WARNING" enabled_by_default="false" />

59
app/src/main/cpp/zenith/eeiv/cop0.h
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@ -8,76 +8,29 @@ namespace zenith::eeiv {
union Cop0Status {
u32 m_rawStatus{};
struct {
u32 interruptEnable: 1;
u32 exceptionLevel: 1;
u32 errorLevel: 1;
// kernelPr == 0 -> Kernel mode
// kernelPr == 1 -> Supervisor mode
// kernelPr == 2 -> User mode
u32 kernelPr: 2;
u32: 5;
u32 interruption0: 1;
u32 interruption1: 1;
u32 busCouldFail: 1;
u32: 2;
u32 interruption5: 1;
u32 interrupt99999: 1;
u32 edi: 1;
u32 cacheHit: 1;
u32: 3;
u32 bev: 1;
u32 dev: 1;
u32 unknownYet: 4;
u32 copUsable: 4;
u8 copUsable;
};
};
union CoProcessor0 {
public:
CoProcessor0();
CoProcessor0(CoProcessor0&& copMove) = delete;
CoProcessor0(CoProcessor0& copCopy) = delete;
CoProcessor0(CoProcessor0&&) = delete;
CoProcessor0(CoProcessor0&) = delete;
#pragma pack(push, 4)
struct {
// The arrays of hwReservedX are all the registers reserved by the hardware manufacturer
u32 index;
u32 random;
u32 entryLo0;
u32 entryLo1;
u32 context;
u32 pageMask;
u32 wired;
u32 hwReserved0[1];
u32 badVAddress;
u32 count;
u32 entryHi;
u32 compare;
Cop0Status status;
u32 cause;
u32 epc;
// The codenamed pRid register determines in the very early boot process for the BIOS
// which processor it is currently running on, whether it's on the EE or the PSX
Cop0Status status;
u32 pRid;
u32 config;
u32 hwReserved1[6];
u32 badPAddress;
u32 debug;
u32 perf;
u32 hwReserved2[2];
u32 tagLo;
u32 tagHi;
u32 errorEPC;
};
#pragma pack(pop)
private:
u32 m_copGPRs[cop0RegsCount]{};
u32 m_copGPRs[2];
};
static_assert(offsetof(CoProcessor0, pRid) == sizeof(u32) * 15);
static_assert(offsetof(CoProcessor0, pRid) == sizeof(u32) * 1);
static_assert(sizeof(u32) * cop0RegsCount == 128);
}

10
app/src/main/cpp/zenith/eeiv/ee_engine.cpp
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@ -6,21 +6,17 @@
namespace zenith::eeiv {
EEMipsCore::EEMipsCore(const std::shared_ptr<console::GlobalMemory>& glbRef)
: m_glbRAM(glbRef),
: m_glbRDRAM(glbRef),
m_eeTLB(std::make_unique<TLBCache>(glbRef))
{
m_GPRs = new eeRegister[countOfGPRs];
m_eeNearCache = new EECacheLine[countOfCacheLines];
switch (m_eeExecMode) {
case EEExecutionMode::CachedInterpreter:
if (m_proCPUMode == EEExecutionMode::CachedInterpreter)
m_eeExecutor = std::make_unique<casper::EEInterpreter>(*this);
break;
case EEExecutionMode::JitRe:
else if (m_proCPUMode == EEExecutionMode::JitRe)
m_eeExecutor = std::make_unique<tokyo3::EEArm64Jitter>(*this);
break;
}
resetCore();
}

4
app/src/main/cpp/zenith/eeiv/ee_engine.h
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@ -25,10 +25,10 @@ namespace zenith::eeiv {
void resetCore();
EEExecutionMode m_eeExecMode{EEExecutionMode::CachedInterpreter};
EEExecutionMode m_proCPUMode{EEExecutionMode::CachedInterpreter};
private:
std::shared_ptr<console::GlobalMemory> m_glbRAM;
std::shared_ptr<console::GlobalMemory> m_glbRDRAM;
union eeRegister {
eeRegister()
: dw{0, 0}

1
app/src/main/cpp/zenith/eeiv/ee_handler.h
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@ -1,7 +1,6 @@
#pragma once
#include <impl_types.h>
namespace zenith::eeiv {
class EEMipsCore;

6
app/src/main/cpp/zenith/eeiv/mmu_tlb.cpp
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@ -26,17 +26,15 @@ namespace zenith::eeiv {
// Kernel page segments are not mapped in the TLB; we need to pass physical addresses
// directly to the table entries
// kseg0 | 80000000h-9fffffffh | Kernel, directly-mapped, cached
// kseg1 | a0000000h-bfffffffh | Kernel, directly-mapped, uncached
for (auto segmentPage{kUnmapStart}; segmentPage != kUnmapEnd; segmentPage += 4096) {
auto kVTable{segmentPage / 4096};
PaperRtAssert(kVTable < 1024 * 1024, "");
m_kernelVTLB[kVTable] = choiceMemSrc(segmentPage & (0x20000000 - 1));
if (segmentPage < 0xa0000000)
m_tlbInfo[kVTable].c0 = TLBCacheMode::Cached;
m_tlbInfo[kVTable].ccMode0 = TLBCacheMode::Cached;
else
m_tlbInfo[kVTable].c0 = TLBCacheMode::Uncached;
m_tlbInfo[kVTable].ccMode0 = TLBCacheMode::Uncached;
}
}

24
app/src/main/cpp/zenith/eeiv/mmu_tlb.h
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@ -4,6 +4,8 @@
#include <link/global_memory.h>
// kuseg | 00000000h-7fffffffh | User, TLB-mapped
// kseg0 | 80000000h-9fffffffh | Kernel, directly-mapped, cached
// kseg1 | a0000000h-bfffffffh | Kernel, directly-mapped, uncached
namespace zenith::eeiv {
enum TLBCacheMode : u32 {
Invalid = 0b00,
@ -14,25 +16,9 @@ namespace zenith::eeiv {
};
struct TLBPageEntry {
u32 v0: 1;
u32 d0: 1;
TLBCacheMode c0: 3{TLBCacheMode::Invalid};
u32 pfn0: 19;
u8 hwReserved0;
u32 v1: 1;
u32 d1: 1;
u32 c1: 1;
u32 hwReserved1: 2;
u32 pfn1: 19;
u32 hwReserved2: 5;
// S - Scratchpad. When set, the virtual mapping goes to scratchpad instead of main memory
u32 s: 1;
u32 aSID: 7;
u32 hwReserved3: 4;
u32 g: 2;
u32 vpn2: 18;
u32 hwReserved4: 12;
u32 mask: 11;
TLBCacheMode ccMode0{TLBCacheMode::Invalid};
// Scratchpad. When set, the virtual mapping goes to scratchpad instead of main memory
bool scratchpad;
};
class TLBCache {