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https://github.com/stenzek/duckstation.git
synced 2024-11-23 05:49:43 +00:00
CPU: Implement alignment (memory) exception
This commit is contained in:
Connor McLaughlin
parent
0726095f00
commit
32a36ef1bc
@ -48,46 +48,54 @@ void Core::SetPC(u32 new_pc)
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FlushPipeline();
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}
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u8 Core::ReadMemoryByte(VirtualMemoryAddress addr)
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bool Core::ReadMemoryByte(VirtualMemoryAddress addr, u8* value)
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{
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u32 value;
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DoMemoryAccess<MemoryAccessType::Read, MemoryAccessSize::Byte, false, true>(addr, value);
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return Truncate8(value);
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u32 temp = 0;
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const bool result = DoMemoryAccess<MemoryAccessType::Read, MemoryAccessSize::Byte, false, true>(addr, temp);
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*value = Truncate8(temp);
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return result;
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}
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u16 Core::ReadMemoryHalfWord(VirtualMemoryAddress addr)
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bool Core::ReadMemoryHalfWord(VirtualMemoryAddress addr, u16* value)
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{
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Assert(Common::IsAlignedPow2(addr, 2));
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u32 value;
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DoMemoryAccess<MemoryAccessType::Read, MemoryAccessSize::HalfWord, false, true>(addr, value);
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return Truncate16(value);
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if (!DoAlignmentCheck<MemoryAccessType::Read, MemoryAccessSize::HalfWord>(addr))
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return false;
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u32 temp = 0;
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const bool result = DoMemoryAccess<MemoryAccessType::Read, MemoryAccessSize::HalfWord, false, true>(addr, temp);
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*value = Truncate16(temp);
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return result;
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}
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u32 Core::ReadMemoryWord(VirtualMemoryAddress addr)
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bool Core::ReadMemoryWord(VirtualMemoryAddress addr, u32* value)
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{
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Assert(Common::IsAlignedPow2(addr, 4));
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u32 value;
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DoMemoryAccess<MemoryAccessType::Read, MemoryAccessSize::Word, false, true>(addr, value);
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return value;
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if (!DoAlignmentCheck<MemoryAccessType::Read, MemoryAccessSize::Word>(addr))
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return false;
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return DoMemoryAccess<MemoryAccessType::Read, MemoryAccessSize::Word, false, true>(addr, *value);
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}
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void Core::WriteMemoryByte(VirtualMemoryAddress addr, u8 value)
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bool Core::WriteMemoryByte(VirtualMemoryAddress addr, u8 value)
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{
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u32 value32 = ZeroExtend32(value);
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DoMemoryAccess<MemoryAccessType::Write, MemoryAccessSize::Byte, false, true>(addr, value32);
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u32 temp = ZeroExtend32(value);
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return DoMemoryAccess<MemoryAccessType::Write, MemoryAccessSize::Byte, false, true>(addr, temp);
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}
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void Core::WriteMemoryHalfWord(VirtualMemoryAddress addr, u16 value)
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bool Core::WriteMemoryHalfWord(VirtualMemoryAddress addr, u16 value)
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{
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Assert(Common::IsAlignedPow2(addr, 2));
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u32 value32 = ZeroExtend32(value);
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DoMemoryAccess<MemoryAccessType::Write, MemoryAccessSize::HalfWord, false, true>(addr, value32);
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if (!DoAlignmentCheck<MemoryAccessType::Write, MemoryAccessSize::HalfWord>(addr))
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return false;
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u32 temp = ZeroExtend32(value);
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return DoMemoryAccess<MemoryAccessType::Write, MemoryAccessSize::HalfWord, false, true>(addr, temp);
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}
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void Core::WriteMemoryWord(VirtualMemoryAddress addr, u32 value)
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bool Core::WriteMemoryWord(VirtualMemoryAddress addr, u32 value)
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{
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Assert(Common::IsAlignedPow2(addr, 4));
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DoMemoryAccess<MemoryAccessType::Write, MemoryAccessSize::Word, false, true>(addr, value);
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if (!DoAlignmentCheck<MemoryAccessType::Write, MemoryAccessSize::Word>(addr))
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return false;
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return DoMemoryAccess<MemoryAccessType::Write, MemoryAccessSize::Word, false, true>(addr, value);
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}
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bool Core::SafeReadMemoryByte(VirtualMemoryAddress addr, u8* value)
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@ -134,9 +142,9 @@ void Core::Branch(u32 target)
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m_branched = true;
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}
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void Core::RaiseException(u32 inst_pc, Exception excode)
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void Core::RaiseException(Exception excode)
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{
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m_cop0_regs.EPC = m_in_branch_delay_slot ? (inst_pc - UINT32_C(4)) : inst_pc;
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m_cop0_regs.EPC = m_in_branch_delay_slot ? (m_current_instruction_pc - UINT32_C(4)) : m_current_instruction_pc;
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m_cop0_regs.cause.Excode = excode;
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m_cop0_regs.cause.BD = m_in_branch_delay_slot;
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@ -222,7 +230,7 @@ void Core::Execute()
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{
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// now executing the instruction we previously fetched
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const Instruction inst = m_next_instruction;
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const u32 inst_pc = m_regs.pc;
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m_current_instruction_pc = m_regs.pc;
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// fetch the next instruction
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FetchInstruction();
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@ -232,7 +240,7 @@ void Core::Execute()
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m_branched = false;
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// execute the instruction we previously fetched
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ExecuteInstruction(inst, inst_pc);
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ExecuteInstruction(inst);
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// next load delay
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m_load_delay_reg = m_next_load_delay_reg;
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@ -249,7 +257,7 @@ void Core::FetchInstruction()
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m_regs.npc += sizeof(m_next_instruction.bits);
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}
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void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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void Core::ExecuteInstruction(Instruction inst)
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{
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#if 0
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if (inst_pc == 0xBFC06FF0)
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@ -260,7 +268,7 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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#endif
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if (TRACE_EXECUTION)
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PrintInstruction(inst.bits, inst_pc);
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PrintInstruction(inst.bits, m_current_instruction_pc);
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switch (inst.op)
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{
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@ -348,7 +356,7 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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const u32 new_value = old_value + add_value;
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if (AddOverflow(old_value, add_value, new_value))
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{
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RaiseException(inst_pc, Exception::Ov);
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RaiseException(Exception::Ov);
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return;
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}
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@ -370,7 +378,7 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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const u32 new_value = old_value - sub_value;
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if (SubOverflow(old_value, sub_value, new_value))
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{
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RaiseException(inst_pc, Exception::Ov);
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RaiseException(Exception::Ov);
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return;
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}
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@ -507,7 +515,7 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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case InstructionFunct::syscall:
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{
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RaiseException(inst_pc, Exception::Syscall);
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RaiseException(Exception::Syscall);
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}
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break;
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@ -549,7 +557,7 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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const u32 new_value = old_value + add_value;
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if (AddOverflow(old_value, add_value, new_value))
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{
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RaiseException(inst_pc, Exception::Ov);
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RaiseException(Exception::Ov);
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return;
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}
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@ -580,7 +588,10 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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case InstructionOp::lb:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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const u8 value = ReadMemoryByte(addr);
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u8 value;
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if (!ReadMemoryByte(addr, &value))
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return;
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WriteRegDelayed(inst.i.rt, SignExtend32(value));
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}
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break;
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@ -588,7 +599,10 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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case InstructionOp::lh:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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const u16 value = ReadMemoryHalfWord(addr);
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u16 value;
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if (!ReadMemoryHalfWord(addr, &value))
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return;
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WriteRegDelayed(inst.i.rt, SignExtend32(value));
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}
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break;
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@ -596,7 +610,10 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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case InstructionOp::lw:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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const u32 value = ReadMemoryWord(addr);
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u32 value;
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if (!ReadMemoryWord(addr, &value))
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return;
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WriteRegDelayed(inst.i.rt, value);
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}
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break;
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@ -604,7 +621,10 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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case InstructionOp::lbu:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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const u8 value = ReadMemoryByte(addr);
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u8 value;
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if (!ReadMemoryByte(addr, &value))
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return;
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WriteRegDelayed(inst.i.rt, ZeroExtend32(value));
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}
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break;
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@ -612,7 +632,10 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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case InstructionOp::lhu:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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const u16 value = ReadMemoryHalfWord(addr);
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u16 value;
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if (!ReadMemoryHalfWord(addr, &value))
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return;
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WriteRegDelayed(inst.i.rt, ZeroExtend32(value));
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}
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break;
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@ -622,7 +645,9 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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const VirtualMemoryAddress aligned_addr = addr & ~UINT32_C(3);
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const u32 aligned_value = ReadMemoryWord(aligned_addr);
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u32 aligned_value;
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if (!ReadMemoryWord(aligned_addr, &aligned_value))
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return;
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// note: bypasses load delay on the read
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const u32 existing_value = m_regs.r[static_cast<u8>(inst.i.rt.GetValue())];
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@ -672,9 +697,11 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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const VirtualMemoryAddress aligned_addr = addr & ~UINT32_C(3);
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const u32 mem_value = ReadMemoryWord(aligned_addr);
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const u32 reg_value = ReadReg(inst.i.rt);
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const u8 shift = (Truncate8(addr) & u8(3)) * u8(8);
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u32 mem_value;
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if (!ReadMemoryWord(aligned_addr, &mem_value))
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return;
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u32 new_value;
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if (inst.op == InstructionOp::swl)
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@ -760,11 +787,11 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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if (!m_cop0_regs.sr.CU0 && InUserMode())
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{
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Log_WarningPrintf("Coprocessor 0 not present in user mode");
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RaiseException(inst_pc, Exception::CpU);
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RaiseException(Exception::CpU);
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return;
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}
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ExecuteCop0Instruction(inst, inst_pc);
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ExecuteCop0Instruction(inst);
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}
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break;
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@ -772,7 +799,7 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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case InstructionOp::cop1:
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case InstructionOp::cop2:
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{
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RaiseException(inst_pc, Exception::CpU);
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RaiseException(Exception::CpU);
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}
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break;
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@ -788,7 +815,7 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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}
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}
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void Core::ExecuteCop0Instruction(Instruction inst, u32 inst_pc)
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void Core::ExecuteCop0Instruction(Instruction inst)
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{
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switch (inst.cop.cop0_op())
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{
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@ -45,15 +45,18 @@ private:
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template<MemoryAccessType type, MemoryAccessSize size, bool is_instruction_fetch, bool raise_exceptions>
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bool DoMemoryAccess(VirtualMemoryAddress address, u32& value);
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template<MemoryAccessType type, MemoryAccessSize size>
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bool DoAlignmentCheck(VirtualMemoryAddress address);
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template<MemoryAccessType type, MemoryAccessSize size>
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void DoScratchpadAccess(PhysicalMemoryAddress address, u32& value);
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u8 ReadMemoryByte(VirtualMemoryAddress addr);
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u16 ReadMemoryHalfWord(VirtualMemoryAddress addr);
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u32 ReadMemoryWord(VirtualMemoryAddress addr);
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void WriteMemoryByte(VirtualMemoryAddress addr, u8 value);
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void WriteMemoryHalfWord(VirtualMemoryAddress addr, u16 value);
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void WriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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bool ReadMemoryByte(VirtualMemoryAddress addr, u8* value);
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bool ReadMemoryHalfWord(VirtualMemoryAddress addr, u16* value);
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bool ReadMemoryWord(VirtualMemoryAddress addr, u32* value);
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bool WriteMemoryByte(VirtualMemoryAddress addr, u8 value);
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bool WriteMemoryHalfWord(VirtualMemoryAddress addr, u16 value);
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bool WriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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// state helpers
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bool InUserMode() const { return m_cop0_regs.sr.KUc; }
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@ -63,10 +66,10 @@ private:
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// Fetches the instruction at m_regs.npc
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void FetchInstruction();
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void ExecuteInstruction(Instruction inst, u32 inst_pc);
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void ExecuteCop0Instruction(Instruction inst, u32 inst_pc);
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void ExecuteInstruction(Instruction inst);
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void ExecuteCop0Instruction(Instruction inst);
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void Branch(u32 target);
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void RaiseException(u32 inst_pc, Exception excode);
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void RaiseException(Exception excode);
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// clears pipeline of load/branch delays
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void FlushPipeline();
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@ -87,6 +90,9 @@ private:
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bool m_in_branch_delay_slot = false;
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bool m_branched = false;
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// address of the instruction currently being executed
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u32 m_current_instruction_pc = 0;
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// load delays
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Reg m_load_delay_reg = Reg::count;
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u32 m_load_delay_old_value = 0;
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@ -106,6 +106,29 @@ bool Core::DoMemoryAccess(VirtualMemoryAddress address, u32& value)
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}
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}
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template<MemoryAccessType type, MemoryAccessSize size>
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bool CPU::Core::DoAlignmentCheck(VirtualMemoryAddress address)
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{
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if constexpr (size == MemoryAccessSize::HalfWord)
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{
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if ((address & UINT32_C(1)) == 0)
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return true;
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}
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else if constexpr (size == MemoryAccessSize::Word)
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{
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if ((address & UINT32_C(3)) == 0)
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return true;
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}
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else
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{
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return true;
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}
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m_cop0_regs.BadVaddr = address;
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RaiseException(type == MemoryAccessType::Read ? Exception::AdEL : Exception::AdES);
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return false;
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}
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template<MemoryAccessType type, MemoryAccessSize size>
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void CPU::Core::DoScratchpadAccess(PhysicalMemoryAddress address, u32& value)
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{
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