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https://github.com/stenzek/duckstation.git
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CPU: Implement cop0 execution and data breakpoints
This commit is contained in:
Connor McLaughlin
parent
22fdd80cc3
commit
442b801d39
@ -23,7 +23,6 @@ static void SetPC(u32 new_pc);
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static void UpdateLoadDelay();
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static void Branch(u32 target);
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static void FlushPipeline();
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static void UpdateDebugDispatcherFlag();
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State g_state;
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bool g_using_interpreter = false;
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@ -227,34 +226,13 @@ ALWAYS_INLINE_RELEASE void Branch(u32 target)
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g_state.branch_was_taken = true;
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}
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ALWAYS_INLINE static u32 GetExceptionVector(Exception excode)
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ALWAYS_INLINE static u32 GetExceptionVector(bool debug_exception = false)
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{
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const u32 base = g_state.cop0_regs.sr.BEV ? UINT32_C(0xbfc00100) : UINT32_C(0x80000000);
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#if 0
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// apparently this isn't correct...
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switch (excode)
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{
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case Exception::BP:
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return base | UINT32_C(0x00000040);
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default:
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return base | UINT32_C(0x00000080);
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}
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#else
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return base | UINT32_C(0x00000080);
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#endif
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return base | (debug_exception ? UINT32_C(0x00000040) : UINT32_C(0x00000080));
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}
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void RaiseException(Exception excode)
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{
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RaiseException(Cop0Registers::CAUSE::MakeValueForException(excode, g_state.current_instruction_in_branch_delay_slot,
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g_state.current_instruction_was_branch_taken,
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g_state.current_instruction.cop.cop_n),
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g_state.current_instruction_pc);
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}
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void RaiseException(u32 CAUSE_bits, u32 EPC)
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ALWAYS_INLINE_RELEASE static void RaiseException(u32 CAUSE_bits, u32 EPC, u32 vector)
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{
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g_state.cop0_regs.EPC = EPC;
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g_state.cop0_regs.cause.bits = (g_state.cop0_regs.cause.bits & ~Cop0Registers::CAUSE::EXCEPTION_WRITE_MASK) |
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@ -264,10 +242,10 @@ void RaiseException(u32 CAUSE_bits, u32 EPC)
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if (g_state.cop0_regs.cause.Excode != Exception::INT && g_state.cop0_regs.cause.Excode != Exception::Syscall &&
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g_state.cop0_regs.cause.Excode != Exception::BP)
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{
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Log_DebugPrintf("Exception %u at 0x%08X (epc=0x%08X, BD=%s, CE=%u)",
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static_cast<u8>(g_state.cop0_regs.cause.Excode.GetValue()), g_state.current_instruction_pc,
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g_state.cop0_regs.EPC, g_state.cop0_regs.cause.BD ? "true" : "false",
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g_state.cop0_regs.cause.CE.GetValue());
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Log_DevPrintf("Exception %u at 0x%08X (epc=0x%08X, BD=%s, CE=%u)",
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static_cast<u8>(g_state.cop0_regs.cause.Excode.GetValue()), g_state.current_instruction_pc,
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g_state.cop0_regs.EPC, g_state.cop0_regs.cause.BD ? "true" : "false",
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g_state.cop0_regs.cause.CE.GetValue());
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DisassembleAndPrint(g_state.current_instruction_pc, 4, 0);
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if (s_trace_to_log)
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{
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@ -291,11 +269,36 @@ void RaiseException(u32 CAUSE_bits, u32 EPC)
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g_state.cop0_regs.sr.mode_bits <<= 2;
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// flush the pipeline - we don't want to execute the previously fetched instruction
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g_state.regs.npc = GetExceptionVector(g_state.cop0_regs.cause.Excode);
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g_state.regs.npc = vector;
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g_state.exception_raised = true;
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FlushPipeline();
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}
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ALWAYS_INLINE_RELEASE static void DispatchCop0Breakpoint()
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{
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// When a breakpoint address match occurs the PSX jumps to 80000040h (ie. unlike normal exceptions, not to 80000080h).
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// The Excode value in the CAUSE register is set to 09h (same as BREAK opcode), and EPC contains the return address,
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// as usually. One of the first things to be done in the exception handler is to disable breakpoints (eg. if the
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// any-jump break is enabled, then it must be disabled BEFORE jumping from 80000040h to the actual exception handler).
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RaiseException(Cop0Registers::CAUSE::MakeValueForException(
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Exception::BP, g_state.current_instruction_in_branch_delay_slot,
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g_state.current_instruction_was_branch_taken, g_state.current_instruction.cop.cop_n),
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g_state.current_instruction_pc, GetExceptionVector(true));
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}
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void RaiseException(u32 CAUSE_bits, u32 EPC)
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{
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RaiseException(CAUSE_bits, EPC, GetExceptionVector());
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}
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void RaiseException(Exception excode)
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{
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RaiseException(Cop0Registers::CAUSE::MakeValueForException(excode, g_state.current_instruction_in_branch_delay_slot,
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g_state.current_instruction_was_branch_taken,
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g_state.current_instruction.cop.cop_n),
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g_state.current_instruction_pc, GetExceptionVector());
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}
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void SetExternalInterrupt(u8 bit)
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{
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g_state.cop0_regs.cause.Ip |= static_cast<u8>(1u << bit);
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@ -466,6 +469,7 @@ ALWAYS_INLINE_RELEASE static void WriteCop0Reg(Cop0Reg reg, u32 value)
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g_state.cop0_regs.dcic.bits =
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(g_state.cop0_regs.dcic.bits & ~Cop0Registers::DCIC::WRITE_MASK) | (value & Cop0Registers::DCIC::WRITE_MASK);
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Log_WarningPrintf("COP0 DCIC <- %08X (now %08X)", value, g_state.cop0_regs.dcic.bits);
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UpdateDebugDispatcherFlag();
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}
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break;
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@ -488,12 +492,83 @@ ALWAYS_INLINE_RELEASE static void WriteCop0Reg(Cop0Reg reg, u32 value)
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break;
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default:
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Log_DevPrintf("Unknown COP0 reg %u", ZeroExtend32(static_cast<u8>(reg)));
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Log_WarningPrintf("Unknown COP0 reg write %u (%08X)", ZeroExtend32(static_cast<u8>(reg)), value);
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break;
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}
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}
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static void PrintInstruction(u32 bits, u32 pc, Registers* regs)
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ALWAYS_INLINE_RELEASE void Cop0ExecutionBreakpointCheck()
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{
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if (!g_state.cop0_regs.dcic.ExecutionBreakpointsEnabled())
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return;
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const u32 pc = g_state.current_instruction_pc;
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const u32 bpc = g_state.cop0_regs.BPC;
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const u32 bpcm = g_state.cop0_regs.BPCM;
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// Break condition is "((PC XOR BPC) AND BPCM)=0".
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if (bpcm == 0 || ((pc ^ bpc) & bpcm) != 0u)
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return;
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Log_DevPrintf("Cop0 execution breakpoint at %08X", pc);
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g_state.cop0_regs.dcic.status_any_break = true;
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g_state.cop0_regs.dcic.status_bpc_code_break = true;
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DispatchCop0Breakpoint();
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}
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template<MemoryAccessType type>
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ALWAYS_INLINE_RELEASE void Cop0DataBreakpointCheck(VirtualMemoryAddress address)
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{
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if constexpr (type == MemoryAccessType::Read)
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{
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if (!g_state.cop0_regs.dcic.DataReadBreakpointsEnabled())
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return;
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}
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else
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{
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if (!g_state.cop0_regs.dcic.DataWriteBreakpointsEnabled())
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return;
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}
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// Break condition is "((addr XOR BDA) AND BDAM)=0".
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const u32 bda = g_state.cop0_regs.BDA;
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const u32 bdam = g_state.cop0_regs.BDAM;
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if (bdam == 0 || ((address ^ bda) & bdam) != 0u)
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return;
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Log_DevPrintf("Cop0 data breakpoint for %08X at %08X", address, g_state.current_instruction_pc);
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g_state.cop0_regs.dcic.status_any_break = true;
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g_state.cop0_regs.dcic.status_bda_data_break = true;
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if constexpr (type == MemoryAccessType::Read)
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g_state.cop0_regs.dcic.status_bda_data_read_break = true;
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else
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g_state.cop0_regs.dcic.status_bda_data_write_break = true;
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DispatchCop0Breakpoint();
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}
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static void TracePrintInstruction()
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{
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const u32 pc = g_state.current_instruction_pc;
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const u32 bits = g_state.current_instruction.bits;
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TinyString instr;
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TinyString comment;
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DisassembleInstruction(&instr, pc, bits);
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DisassembleInstructionComment(&comment, pc, bits, &g_state.regs);
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if (!comment.IsEmpty())
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{
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for (u32 i = instr.GetLength(); i < 30; i++)
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instr.AppendCharacter(' ');
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instr.AppendString("; ");
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instr.AppendString(comment);
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}
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std::printf("%08x: %08x %s\n", pc, bits, instr.GetCharArray());
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}
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static void PrintInstruction(u32 bits, u32 pc, Registers* regs, const char* prefix)
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{
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TinyString instr;
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TinyString comment;
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@ -507,7 +582,7 @@ static void PrintInstruction(u32 bits, u32 pc, Registers* regs)
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instr.AppendString(comment);
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}
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std::printf("%08x: %08x %s\n", pc, bits, instr.GetCharArray());
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Log_DevPrintf("%s%08x: %08x %s", prefix, pc, bits, instr.GetCharArray());
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}
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static void LogInstruction(u32 bits, u32 pc, Registers* regs)
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@ -537,11 +612,11 @@ ALWAYS_INLINE static constexpr bool SubOverflow(u32 old_value, u32 sub_value, u3
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return (((new_value ^ old_value) & (old_value ^ sub_value)) & UINT32_C(0x80000000)) != 0;
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}
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void DisassembleAndPrint(u32 addr)
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void DisassembleAndPrint(u32 addr, const char* prefix)
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{
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u32 bits = 0;
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SafeReadMemoryWord(addr, &bits);
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PrintInstruction(bits, addr, &g_state.regs);
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PrintInstruction(bits, addr, &g_state.regs, prefix);
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}
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void DisassembleAndPrint(u32 addr, u32 instructions_before /* = 0 */, u32 instructions_after /* = 0 */)
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@ -549,21 +624,19 @@ void DisassembleAndPrint(u32 addr, u32 instructions_before /* = 0 */, u32 instru
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u32 disasm_addr = addr - (instructions_before * sizeof(u32));
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for (u32 i = 0; i < instructions_before; i++)
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{
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DisassembleAndPrint(disasm_addr);
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DisassembleAndPrint(disasm_addr, "");
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disasm_addr += sizeof(u32);
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}
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std::printf("----> ");
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// <= to include the instruction itself
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for (u32 i = 0; i <= instructions_after; i++)
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{
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DisassembleAndPrint(disasm_addr);
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DisassembleAndPrint(disasm_addr, (i == 0) ? "---->" : "");
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disasm_addr += sizeof(u32);
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}
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}
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template<PGXPMode pgxp_mode>
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template<PGXPMode pgxp_mode, bool debug>
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ALWAYS_INLINE_RELEASE static void ExecuteInstruction()
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{
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restart_instruction:
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@ -579,7 +652,7 @@ restart_instruction:
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#ifdef _DEBUG
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if (TRACE_EXECUTION)
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PrintInstruction(inst.bits, g_state.current_instruction_pc, &g_state.regs);
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TracePrintInstruction();
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#endif
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// Skip nops. Makes PGXP-CPU quicker, but also the regular interpreter.
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@ -1059,6 +1132,9 @@ restart_instruction:
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case InstructionOp::lb:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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if constexpr (debug)
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Cop0DataBreakpointCheck<MemoryAccessType::Read>(addr);
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u8 value;
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if (!ReadMemoryByte(addr, &value))
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return;
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@ -1075,6 +1151,9 @@ restart_instruction:
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case InstructionOp::lh:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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if constexpr (debug)
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Cop0DataBreakpointCheck<MemoryAccessType::Read>(addr);
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u16 value;
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if (!ReadMemoryHalfWord(addr, &value))
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return;
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@ -1090,6 +1169,9 @@ restart_instruction:
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case InstructionOp::lw:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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if constexpr (debug)
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Cop0DataBreakpointCheck<MemoryAccessType::Read>(addr);
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u32 value;
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if (!ReadMemoryWord(addr, &value))
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return;
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@ -1104,6 +1186,9 @@ restart_instruction:
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case InstructionOp::lbu:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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if constexpr (debug)
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Cop0DataBreakpointCheck<MemoryAccessType::Read>(addr);
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u8 value;
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if (!ReadMemoryByte(addr, &value))
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return;
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@ -1119,6 +1204,9 @@ restart_instruction:
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case InstructionOp::lhu:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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if constexpr (debug)
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Cop0DataBreakpointCheck<MemoryAccessType::Read>(addr);
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u16 value;
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if (!ReadMemoryHalfWord(addr, &value))
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return;
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@ -1136,6 +1224,9 @@ restart_instruction:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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const VirtualMemoryAddress aligned_addr = addr & ~UINT32_C(3);
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if constexpr (debug)
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Cop0DataBreakpointCheck<MemoryAccessType::Read>(addr);
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u32 aligned_value;
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if (!ReadMemoryWord(aligned_addr, &aligned_value))
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return;
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@ -1165,6 +1256,9 @@ restart_instruction:
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case InstructionOp::sb:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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if constexpr (debug)
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Cop0DataBreakpointCheck<MemoryAccessType::Write>(addr);
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const u8 value = Truncate8(ReadReg(inst.i.rt));
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WriteMemoryByte(addr, value);
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@ -1176,6 +1270,9 @@ restart_instruction:
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case InstructionOp::sh:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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if constexpr (debug)
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Cop0DataBreakpointCheck<MemoryAccessType::Write>(addr);
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const u16 value = Truncate16(ReadReg(inst.i.rt));
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WriteMemoryHalfWord(addr, value);
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@ -1187,6 +1284,9 @@ restart_instruction:
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case InstructionOp::sw:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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if constexpr (debug)
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Cop0DataBreakpointCheck<MemoryAccessType::Write>(addr);
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const u32 value = ReadReg(inst.i.rt);
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WriteMemoryWord(addr, value);
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@ -1200,6 +1300,9 @@ restart_instruction:
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{
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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const VirtualMemoryAddress aligned_addr = addr & ~UINT32_C(3);
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if constexpr (debug)
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Cop0DataBreakpointCheck<MemoryAccessType::Write>(aligned_addr);
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const u32 reg_value = ReadReg(inst.i.rt);
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const u8 shift = (Truncate8(addr) & u8(3)) * u8(8);
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u32 mem_value;
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@ -1508,16 +1611,20 @@ void DispatchInterrupt()
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g_state.regs.pc);
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}
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static void UpdateDebugDispatcherFlag()
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void UpdateDebugDispatcherFlag()
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{
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const bool has_any_breakpoints = !s_breakpoints.empty();
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// TODO: cop0 breakpoints
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const auto& dcic = g_state.cop0_regs.dcic;
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const bool has_cop0_breakpoints =
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dcic.super_master_enable_1 && dcic.super_master_enable_2 && dcic.execution_breakpoint_enable;
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const bool use_debug_dispatcher = has_any_breakpoints || s_trace_to_log;
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const bool use_debug_dispatcher = has_any_breakpoints || has_cop0_breakpoints || s_trace_to_log;
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if (use_debug_dispatcher == g_state.use_debug_dispatcher)
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return;
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Log_DevPrintf("%s debug dispatcher", use_debug_dispatcher ? "Now using" : "No longer using");
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g_state.use_debug_dispatcher = use_debug_dispatcher;
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ForceDispatcherExit();
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}
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@ -1694,7 +1801,7 @@ bool AddStepOutBreakpoint(u32 max_instructions_to_search)
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return false;
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}
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static ALWAYS_INLINE_RELEASE bool BreakpointCheck()
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ALWAYS_INLINE_RELEASE static bool BreakpointCheck()
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{
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const u32 pc = g_state.regs.pc;
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@ -1779,6 +1886,8 @@ static void ExecuteImpl()
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if constexpr (debug)
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{
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Cop0ExecutionBreakpointCheck();
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if (BreakpointCheck())
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{
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// continue is measurably faster than break on msvc for some reason
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@ -1818,7 +1927,7 @@ static void ExecuteImpl()
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#endif
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// execute the instruction we previously fetched
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ExecuteInstruction<pgxp_mode>();
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ExecuteInstruction<pgxp_mode, debug>();
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// next load delay
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UpdateLoadDelay();
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@ -1891,7 +2000,7 @@ void InterpretCachedBlock(const CodeBlock& block)
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g_state.regs.npc += 4;
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// execute the instruction we previously fetched
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ExecuteInstruction<pgxp_mode>();
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ExecuteInstruction<pgxp_mode, false>();
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// next load delay
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UpdateLoadDelay();
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@ -1944,7 +2053,7 @@ void InterpretUncachedBlock()
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}
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// execute the instruction we previously fetched
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ExecuteInstruction<pgxp_mode>();
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ExecuteInstruction<pgxp_mode, false>();
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// next load delay
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UpdateLoadDelay();
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@ -1969,13 +2078,13 @@ namespace Recompiler::Thunks {
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bool InterpretInstruction()
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{
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ExecuteInstruction<PGXPMode::Disabled>();
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ExecuteInstruction<PGXPMode::Disabled, false>();
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return g_state.exception_raised;
|
||||
}
|
||||
|
||||
bool InterpretInstructionPGXP()
|
||||
{
|
||||
ExecuteInstruction<PGXPMode::Memory>();
|
||||
ExecuteInstruction<PGXPMode::Memory, false>();
|
||||
return g_state.exception_raised;
|
||||
}
|
||||
|
||||
|
||||
@ -21,6 +21,7 @@ ALWAYS_INLINE void CheckForPendingInterrupt()
|
||||
}
|
||||
|
||||
void DispatchInterrupt();
|
||||
void UpdateDebugDispatcherFlag();
|
||||
|
||||
// icache stuff
|
||||
ALWAYS_INLINE bool IsCachedAddress(VirtualMemoryAddress address)
|
||||
|
||||
@ -2494,25 +2494,55 @@ bool CodeGenerator::Compile_cop0(const CodeBlockInstruction& cbi)
|
||||
}
|
||||
}
|
||||
|
||||
if (cbi.instruction.cop.CommonOp() == CopCommonInstruction::mtcn &&
|
||||
(reg == Cop0Reg::CAUSE || reg == Cop0Reg::SR))
|
||||
if (cbi.instruction.cop.CommonOp() == CopCommonInstruction::mtcn)
|
||||
{
|
||||
// Emit an interrupt check on load of CAUSE/SR.
|
||||
Value sr_value = m_register_cache.AllocateScratch(RegSize_32);
|
||||
Value cause_value = m_register_cache.AllocateScratch(RegSize_32);
|
||||
if (reg == Cop0Reg::CAUSE || reg == Cop0Reg::SR)
|
||||
{
|
||||
// Emit an interrupt check on load of CAUSE/SR.
|
||||
Value sr_value = m_register_cache.AllocateScratch(RegSize_32);
|
||||
Value cause_value = m_register_cache.AllocateScratch(RegSize_32);
|
||||
|
||||
// m_cop0_regs.sr.IEc && ((m_cop0_regs.cause.Ip & m_cop0_regs.sr.Im) != 0)
|
||||
LabelType no_interrupt;
|
||||
EmitLoadCPUStructField(sr_value.host_reg, sr_value.size, offsetof(State, cop0_regs.sr.bits));
|
||||
EmitLoadCPUStructField(cause_value.host_reg, cause_value.size, offsetof(State, cop0_regs.cause.bits));
|
||||
EmitBranchIfBitClear(sr_value.host_reg, sr_value.size, 0, &no_interrupt);
|
||||
m_register_cache.InhibitAllocation();
|
||||
EmitAnd(sr_value.host_reg, sr_value.host_reg, cause_value);
|
||||
EmitTest(sr_value.host_reg, Value::FromConstantU32(0xFF00));
|
||||
EmitConditionalBranch(Condition::Zero, false, &no_interrupt);
|
||||
EmitStoreCPUStructField(offsetof(State, downcount), Value::FromConstantU32(0));
|
||||
EmitBindLabel(&no_interrupt);
|
||||
m_register_cache.UninhibitAllocation();
|
||||
// m_cop0_regs.sr.IEc && ((m_cop0_regs.cause.Ip & m_cop0_regs.sr.Im) != 0)
|
||||
LabelType no_interrupt;
|
||||
EmitLoadCPUStructField(sr_value.host_reg, sr_value.size, offsetof(State, cop0_regs.sr.bits));
|
||||
EmitLoadCPUStructField(cause_value.host_reg, cause_value.size, offsetof(State, cop0_regs.cause.bits));
|
||||
EmitBranchIfBitClear(sr_value.host_reg, sr_value.size, 0, &no_interrupt);
|
||||
m_register_cache.InhibitAllocation();
|
||||
EmitAnd(sr_value.host_reg, sr_value.host_reg, cause_value);
|
||||
EmitTest(sr_value.host_reg, Value::FromConstantU32(0xFF00));
|
||||
EmitConditionalBranch(Condition::Zero, false, &no_interrupt);
|
||||
EmitStoreCPUStructField(offsetof(State, downcount), Value::FromConstantU32(0));
|
||||
EmitBindLabel(&no_interrupt);
|
||||
m_register_cache.UninhibitAllocation();
|
||||
}
|
||||
else if (reg == Cop0Reg::DCIC)
|
||||
{
|
||||
Value dcic_value = m_register_cache.AllocateScratch(RegSize_32);
|
||||
m_register_cache.InhibitAllocation();
|
||||
|
||||
// if ((dcic & master_enable_bits) != master_enable_bits) goto not_enabled;
|
||||
LabelType not_enabled;
|
||||
EmitLoadCPUStructField(dcic_value.host_reg, dcic_value.size, offsetof(State, cop0_regs.dcic.bits));
|
||||
EmitAnd(dcic_value.host_reg, dcic_value.host_reg,
|
||||
Value::FromConstantU32(Cop0Registers::DCIC::MASTER_ENABLE_BITS));
|
||||
EmitConditionalBranch(Condition::NotEqual, false, dcic_value.host_reg,
|
||||
Value::FromConstantU32(Cop0Registers::DCIC::MASTER_ENABLE_BITS), ¬_enabled);
|
||||
|
||||
// if ((dcic & breakpoint_bits) == 0) goto not_enabled;
|
||||
EmitLoadCPUStructField(dcic_value.host_reg, dcic_value.size, offsetof(State, cop0_regs.dcic.bits));
|
||||
EmitTest(dcic_value.host_reg, Value::FromConstantU32(Cop0Registers::DCIC::ANY_BREAKPOINTS_ENABLED_BITS));
|
||||
EmitConditionalBranch(Condition::Zero, false, ¬_enabled);
|
||||
|
||||
m_register_cache.UninhibitAllocation();
|
||||
|
||||
// exit block early if enabled
|
||||
m_register_cache.PushState();
|
||||
EmitFunctionCall(nullptr, &CPU::UpdateDebugDispatcherFlag);
|
||||
EmitExceptionExit();
|
||||
m_register_cache.PopState();
|
||||
|
||||
EmitBindLabel(¬_enabled);
|
||||
}
|
||||
}
|
||||
|
||||
InstructionEpilogue(cbi);
|
||||
|
||||
@ -283,8 +283,7 @@ struct Registers
|
||||
};
|
||||
};
|
||||
|
||||
std::optional<VirtualMemoryAddress> GetLoadStoreEffectiveAddress(const Instruction& instruction,
|
||||
const Registers* regs);
|
||||
std::optional<VirtualMemoryAddress> GetLoadStoreEffectiveAddress(const Instruction& instruction, const Registers* regs);
|
||||
|
||||
enum class Cop0Reg : u8
|
||||
{
|
||||
@ -402,6 +401,27 @@ struct Cop0Registers
|
||||
BitField<u32, bool, 31, 1> super_master_enable_2;
|
||||
|
||||
static constexpr u32 WRITE_MASK = 0b1111'1111'1000'0000'1111'0000'0011'1111;
|
||||
|
||||
static constexpr u32 ANY_BREAKPOINTS_ENABLED_BITS = (1u << 24) | (1u << 26) | (1u << 27) | (1u << 28);
|
||||
static constexpr u32 MASTER_ENABLE_BITS = (1u << 23) | (1u << 31);
|
||||
|
||||
constexpr bool ExecutionBreakpointsEnabled() const
|
||||
{
|
||||
const u32 mask = (1u << 23) | (1u << 24) | (1u << 31);
|
||||
return ((bits & mask) == mask);
|
||||
}
|
||||
|
||||
constexpr bool DataReadBreakpointsEnabled() const
|
||||
{
|
||||
const u32 mask = (1u << 23) | (1u << 25) | (1u << 26) | (1u << 31);
|
||||
return ((bits & mask) == mask);
|
||||
}
|
||||
|
||||
constexpr bool DataWriteBreakpointsEnabled() const
|
||||
{
|
||||
const u32 mask = (1u << 23) | (1u << 25) | (1u << 27) | (1u << 31);
|
||||
return ((bits & mask) == mask);
|
||||
}
|
||||
} dcic;
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user