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Skeleton for MDEC

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This commit is contained in:
Connor McLaughlin 2019-09-29 12:51:34 +10:00
parent d47717fdd6
commit a48b856a62
11 changed files with 283 additions and 14 deletions
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21
src/pse/bus.cpp
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@ -9,6 +9,7 @@
#include "dma.h"
#include "gpu.h"
#include "interrupt_controller.h"
#include "mdec.h"
#include "pad.h"
#include "spu.h"
#include "timers.h"
@ -28,7 +29,7 @@ Bus::Bus() = default;
Bus::~Bus() = default;
bool Bus::Initialize(CPU::Core* cpu, DMA* dma, InterruptController* interrupt_controller, GPU* gpu, CDROM* cdrom,
Pad* pad, Timers* timers, SPU* spu)
Pad* pad, Timers* timers, SPU* spu, MDEC* mdec)
{
if (!LoadBIOS())
return false;
@ -41,6 +42,7 @@ bool Bus::Initialize(CPU::Core* cpu, DMA* dma, InterruptController* interrupt_co
m_pad = pad;
m_timers = timers;
m_spu = spu;
m_mdec = mdec;
return true;
}
@ -80,8 +82,7 @@ bool Bus::ReadByte(PhysicalMemoryAddress address, u8* value)
bool Bus::ReadHalfWord(PhysicalMemoryAddress address, u16* value)
{
u32 temp = 0;
const bool result =
DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::HalfWord>(address, temp);
const bool result = DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::HalfWord>(address, temp);
*value = Truncate16(temp);
return result;
}
@ -375,6 +376,20 @@ bool Bus::DoWriteGPU(MemoryAccessSize size, u32 offset, u32 value)
return true;
}
bool Bus::DoReadMDEC(MemoryAccessSize size, u32 offset, u32& value)
{
Assert(size == MemoryAccessSize::Word);
value = m_mdec->ReadRegister(offset);
return true;
}
bool Bus::DoWriteMDEC(MemoryAccessSize size, u32 offset, u32 value)
{
Assert(size == MemoryAccessSize::Word);
m_mdec->WriteRegister(offset, value);
return true;
}
bool Bus::DoReadInterruptController(MemoryAccessSize size, u32 offset, u32& value)
{
FixupUnalignedWordAccessW32(offset, value);

12
src/pse/bus.h
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@ -17,6 +17,7 @@ class CDROM;
class Pad;
class Timers;
class SPU;
class MDEC;
class System;
class Bus
@ -26,7 +27,7 @@ public:
~Bus();
bool Initialize(CPU::Core* cpu, DMA* dma, InterruptController* interrupt_controller, GPU* gpu, CDROM* cdrom, Pad* pad,
Timers* timers, SPU* spu);
Timers* timers, SPU* spu, MDEC* mdec);
void Reset();
bool DoState(StateWrapper& sw);
@ -71,11 +72,14 @@ private:
TIMERS_SIZE = 0x40,
TIMERS_MASK = TIMERS_SIZE - 1,
CDROM_BASE = 0x1F801800,
CDROM_SIZE = 0x04,
CDROM_SIZE = 0x10,
CDROM_MASK = CDROM_SIZE - 1,
GPU_BASE = 0x1F801810,
GPU_SIZE = 0x10,
GPU_MASK = GPU_SIZE - 1,
MDEC_BASE = 0x1F801820,
MDEC_SIZE = 0x10,
MDEC_MASK = MDEC_SIZE - 1,
SPU_BASE = 0x1F801C00,
SPU_SIZE = 0x300,
SPU_MASK = 0x3FF,
@ -143,6 +147,9 @@ private:
bool DoReadGPU(MemoryAccessSize size, u32 offset, u32& value);
bool DoWriteGPU(MemoryAccessSize size, u32 offset, u32 value);
bool DoReadMDEC(MemoryAccessSize size, u32 offset, u32& value);
bool DoWriteMDEC(MemoryAccessSize size, u32 offset, u32 value);
bool DoReadInterruptController(MemoryAccessSize size, u32 offset, u32& value);
bool DoWriteInterruptController(MemoryAccessSize size, u32 offset, u32 value);
@ -163,6 +170,7 @@ private:
Pad* m_pad = nullptr;
Timers* m_timers = nullptr;
SPU* m_spu = nullptr;
MDEC* m_mdec = nullptr;
std::array<u8, 2097152> m_ram{}; // 2MB RAM
std::array<u8, 524288> m_bios{}; // 512K BIOS ROM

9
src/pse/bus.inl
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@ -138,15 +138,16 @@ bool Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
return (type == MemoryAccessType::Read) ? DoReadCDROM(size, address & CDROM_MASK, value) :
DoWriteCDROM(size, address & CDROM_MASK, value);
}
else if (address < GPU_BASE)
{
return DoInvalidAccess(type, size, address, value);
}
else if (address < (GPU_BASE + GPU_SIZE))
{
return (type == MemoryAccessType::Read) ? DoReadGPU(size, address & GPU_MASK, value) :
DoWriteGPU(size, address & GPU_MASK, value);
}
else if (address < (MDEC_BASE + MDEC_SIZE))
{
return (type == MemoryAccessType::Read) ? DoReadMDEC(size, address & MDEC_MASK, value) :
DoWriteMDEC(size, address & MDEC_MASK, value);
}
else if (address < SPU_BASE)
{
return DoInvalidAccess(type, size, address, value);

11
src/pse/dma.cpp
View File

@ -5,6 +5,7 @@
#include "common/state_wrapper.h"
#include "gpu.h"
#include "interrupt_controller.h"
#include "mdec.h"
#include "spu.h"
#include "system.h"
Log_SetChannel(DMA);
@ -14,7 +15,7 @@ DMA::DMA() = default;
DMA::~DMA() = default;
bool DMA::Initialize(System* system, Bus* bus, InterruptController* interrupt_controller, GPU* gpu, CDROM* cdrom,
SPU* spu)
SPU* spu, MDEC* mdec)
{
m_system = system;
m_bus = bus;
@ -22,6 +23,7 @@ bool DMA::Initialize(System* system, Bus* bus, InterruptController* interrupt_co
m_gpu = gpu;
m_cdrom = cdrom;
m_spu = spu;
m_mdec = mdec;
return true;
}
@ -371,8 +373,10 @@ u32 DMA::DMARead(Channel channel, PhysicalMemoryAddress dst_address, u32 remaini
case Channel::SPU:
return m_spu->DMARead();
case Channel::MDECin:
case Channel::MDECout:
return m_mdec->DMARead();
case Channel::MDECin:
case Channel::PIO:
default:
Panic("Unhandled DMA channel read");
@ -393,6 +397,9 @@ void DMA::DMAWrite(Channel channel, u32 value, PhysicalMemoryAddress src_address
break;
case Channel::MDECin:
m_mdec->DMAWrite(value);
break;
case Channel::MDECout:
case Channel::CDROM:
case Channel::PIO:

4
src/pse/dma.h
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@ -11,6 +11,7 @@ class InterruptController;
class GPU;
class CDROM;
class SPU;
class MDEC;
class DMA
{
@ -35,7 +36,7 @@ public:
~DMA();
bool Initialize(System* system, Bus* bus, InterruptController* interrupt_controller, GPU* gpu, CDROM* cdrom,
SPU* spu);
SPU* spu, MDEC* mdec);
void Reset();
bool DoState(StateWrapper& sw);
@ -78,6 +79,7 @@ private:
GPU* m_gpu = nullptr;
CDROM* m_cdrom = nullptr;
SPU* m_spu = nullptr;
MDEC* m_mdec = nullptr;
TickCount m_transfer_ticks = 0;
bool m_transfer_pending = false;

139
src/pse/mdec.cpp Normal file
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@ -0,0 +1,139 @@
#include "mdec.h"
#include "YBaseLib/Log.h"
#include "common/state_wrapper.h"
#include "dma.h"
#include "interrupt_controller.h"
#include "system.h"
Log_SetChannel(MDEC);
MDEC::MDEC() = default;
MDEC::~MDEC() = default;
bool MDEC::Initialize(System* system, DMA* dma)
{
m_system = system;
m_dma = dma;
return true;
}
void MDEC::Reset()
{
SoftReset();
}
bool MDEC::DoState(StateWrapper& sw)
{
sw.Do(&m_status_register.bits);
sw.Do(&m_data_in_fifo);
sw.Do(&m_data_out_fifo);
return !sw.HasError();
}
u32 MDEC::ReadRegister(u32 offset)
{
switch (offset)
{
case 0:
return ReadDataRegister();
case 4:
{
Log_DebugPrintf("MDEC status register -> 0x%08X", m_status_register.bits);
return m_status_register.bits;
}
default:
{
Log_ErrorPrintf("Unknown MDEC register read: 0x%08X", offset);
return UINT32_C(0xFFFFFFFF);
}
}
}
void MDEC::WriteRegister(u32 offset, u32 value)
{
switch (offset)
{
case 0:
{
WriteCommandRegister(value);
return;
}
case 4:
{
Log_DebugPrintf("MDEC control register <- 0x%08X", value);
const ControlRegister cr{value};
if (cr.reset)
SoftReset();
m_status_register.data_in_request = cr.enable_dma_in;
m_status_register.data_out_request = cr.enable_dma_out;
m_dma->SetRequest(DMA::Channel::MDECin, cr.enable_dma_in);
m_dma->SetRequest(DMA::Channel::MDECout, cr.enable_dma_out);
return;
}
default:
{
Log_ErrorPrintf("Unknown MDEC register write: 0x%08X <- 0x%08X", offset, value);
return;
}
}
}
u32 MDEC::DMARead()
{
return ReadDataRegister();
}
void MDEC::DMAWrite(u32 value)
{
WriteCommandRegister(value);
}
void MDEC::SoftReset()
{
m_status_register = {};
m_data_in_fifo.Clear();
m_data_out_fifo.Clear();
UpdateStatusRegister();
}
void MDEC::UpdateStatusRegister()
{
m_status_register.data_out_fifo_empty = m_data_out_fifo.IsEmpty();
m_status_register.data_in_fifo_full = m_data_in_fifo.IsFull();
}
void MDEC::WriteCommandRegister(u32 value)
{
Log_DebugPrintf("MDEC command/data register <- 0x%08X", value);
m_data_in_fifo.Push(value);
HandleCommand();
UpdateStatusRegister();
}
u32 MDEC::ReadDataRegister()
{
if (m_data_out_fifo.IsEmpty())
{
Log_WarningPrintf("MDEC data out FIFO empty on read");
return UINT32_C(0xFFFFFFFF);
}
const u32 value = m_data_out_fifo.Pop();
UpdateStatusRegister();
return value;
}
void MDEC::HandleCommand()
{
Log_DebugPrintf("MDEC command: 0x%08X", m_data_in_fifo.Peek(0));
}

81
src/pse/mdec.h Normal file
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@ -0,0 +1,81 @@
#pragma once
#include "common/bitfield.h"
#include "common/fifo_queue.h"
#include "types.h"
#include <string>
#include <vector>
class StateWrapper;
class System;
class DMA;
class MDEC
{
public:
MDEC();
~MDEC();
bool Initialize(System* system, DMA* dma);
void Reset();
bool DoState(StateWrapper& sw);
// I/O
u32 ReadRegister(u32 offset);
void WriteRegister(u32 offset, u32 value);
u32 DMARead();
void DMAWrite(u32 value);
private:
static constexpr u32 DATA_IN_FIFO_SIZE = 256;
static constexpr u32 DATA_OUT_FIFO_SIZE = 256;
enum DataOutputDepth : u8
{
DataOutputDepth_4Bit = 0,
DataOutputDepth_8Bit = 1,
DataOutputDepth_24Bit = 2,
DataOutputDepth_15Bit = 3
};
union StatusRegister
{
u32 bits;
BitField<u32, bool, 31, 1> data_out_fifo_empty;
BitField<u32, bool, 30, 1> data_in_fifo_full;
BitField<u32, bool, 29, 1> command_busy;
BitField<u32, bool, 28, 1> data_in_request;
BitField<u32, bool, 27, 1> data_out_request;
BitField<u32, DataOutputDepth, 25, 2> data_output_depth;
BitField<u32, bool, 24, 1> data_output_signed;
BitField<u32, u8, 23, 1> data_output_bit15;
BitField<u32, u8, 16, 3> current_block;
BitField<u32, u16, 0, 16> parameter_words_remaining;
};
union ControlRegister
{
u32 bits;
BitField<u32, bool, 31, 1> reset;
BitField<u32, bool, 30, 1> enable_dma_in;
BitField<u32, bool, 29, 1> enable_dma_out;
};
void SoftReset();
void UpdateStatusRegister();
void WriteCommandRegister(u32 value);
u32 ReadDataRegister();
void HandleCommand();
System* m_system = nullptr;
DMA* m_dma = nullptr;
StatusRegister m_status_register = {};
InlineFIFOQueue<u32, DATA_IN_FIFO_SIZE> m_data_in_fifo;
InlineFIFOQueue<u32, DATA_OUT_FIFO_SIZE> m_data_out_fifo;
};

2
src/pse/pse.vcxproj
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@ -47,6 +47,7 @@
<ClCompile Include="gpu_hw_opengl.cpp" />
<ClCompile Include="host_interface.cpp" />
<ClCompile Include="interrupt_controller.cpp" />
<ClCompile Include="mdec.cpp" />
<ClCompile Include="pad.cpp" />
<ClCompile Include="pad_device.cpp" />
<ClCompile Include="spu.cpp" />
@ -68,6 +69,7 @@
<ClInclude Include="gte_types.h" />
<ClInclude Include="host_interface.h" />
<ClInclude Include="interrupt_controller.h" />
<ClInclude Include="mdec.h" />
<ClInclude Include="pad.h" />
<ClInclude Include="pad_device.h" />
<ClInclude Include="save_state_version.h" />

2
src/pse/pse.vcxproj.filters
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@ -18,6 +18,7 @@
<ClCompile Include="digital_controller.cpp" />
<ClCompile Include="timers.cpp" />
<ClCompile Include="spu.cpp" />
<ClCompile Include="mdec.cpp" />
</ItemGroup>
<ItemGroup>
<ClInclude Include="types.h" />
@ -41,6 +42,7 @@
<ClInclude Include="digital_controller.h" />
<ClInclude Include="timers.h" />
<ClInclude Include="spu.h" />
<ClInclude Include="mdec.h" />
</ItemGroup>
<ItemGroup>
<None Include="cpu_core.inl" />

14
src/pse/system.cpp
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@ -7,6 +7,7 @@
#include "dma.h"
#include "gpu.h"
#include "interrupt_controller.h"
#include "mdec.h"
#include "pad.h"
#include "pad_device.h"
#include "spu.h"
@ -26,6 +27,7 @@ System::System(HostInterface* host_interface) : m_host_interface(host_interface)
m_pad = std::make_unique<Pad>();
m_timers = std::make_unique<Timers>();
m_spu = std::make_unique<SPU>();
m_mdec = std::make_unique<MDEC>();
}
System::~System() = default;
@ -36,12 +38,13 @@ bool System::Initialize()
return false;
if (!m_bus->Initialize(m_cpu.get(), m_dma.get(), m_interrupt_controller.get(), m_gpu.get(), m_cdrom.get(),
m_pad.get(), m_timers.get(), m_spu.get()))
m_pad.get(), m_timers.get(), m_spu.get(), m_mdec.get()))
{
return false;
}
if (!m_dma->Initialize(this, m_bus.get(), m_interrupt_controller.get(), m_gpu.get(), m_cdrom.get(), m_spu.get()))
if (!m_dma->Initialize(this, m_bus.get(), m_interrupt_controller.get(), m_gpu.get(), m_cdrom.get(), m_spu.get(),
m_mdec.get()))
{
return false;
}
@ -64,6 +67,9 @@ bool System::Initialize()
if (!m_spu->Initialize(this, m_dma.get(), m_interrupt_controller.get()))
return false;
if (!m_mdec->Initialize(this, m_dma.get()))
return false;
return true;
}
@ -96,6 +102,9 @@ bool System::DoState(StateWrapper& sw)
if (!sw.DoMarker("SPU") || !m_timers->DoState(sw))
return false;
if (!sw.DoMarker("MDEC") || !m_mdec->DoState(sw))
return false;
return !sw.HasError();
}
@ -110,6 +119,7 @@ void System::Reset()
m_pad->Reset();
m_timers->Reset();
m_spu->Reset();
m_mdec->Reset();
m_frame_number = 1;
}

2
src/pse/system.h
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@ -21,6 +21,7 @@ class Pad;
class PadDevice;
class Timers;
class SPU;
class MDEC;
class System
{
@ -69,6 +70,7 @@ private:
std::unique_ptr<Pad> m_pad;
std::unique_ptr<Timers> m_timers;
std::unique_ptr<SPU> m_spu;
std::unique_ptr<MDEC> m_mdec;
u32 m_frame_number = 1;
u32 m_internal_frame_number = 1;
};