2022-07-07 10:59:55 +00:00
|
|
|
unit emit_SOPK;
|
|
|
|
|
|
|
|
{$mode objfpc}{$H+}
|
|
|
|
|
|
|
|
interface
|
|
|
|
|
|
|
|
uses
|
2024-02-28 19:00:07 +00:00
|
|
|
sysutils,
|
|
|
|
spirv,
|
|
|
|
ps4_pssl,
|
|
|
|
srType,
|
|
|
|
srReg,
|
|
|
|
emit_fetch;
|
2022-07-07 10:59:55 +00:00
|
|
|
|
|
|
|
type
|
2022-09-05 13:30:24 +00:00
|
|
|
TEmit_SOPK=class(TEmitFetch)
|
|
|
|
procedure emit_SOPK;
|
|
|
|
procedure emit_S_MOVK_I32;
|
2022-12-06 19:03:06 +00:00
|
|
|
procedure emit_S_ADDK_I32;
|
2024-02-28 19:00:07 +00:00
|
|
|
procedure emit_S_CMPK_I32(OpId:DWORD);
|
|
|
|
procedure emit_S_CMPK_U32(OpId:DWORD);
|
2022-07-07 10:59:55 +00:00
|
|
|
end;
|
|
|
|
|
|
|
|
implementation
|
|
|
|
|
2022-12-06 19:03:06 +00:00
|
|
|
function SignExtend16(W:Word):Integer; inline;
|
|
|
|
const
|
|
|
|
shift=BitSizeOf(Integer)-BitSizeOf(Word);
|
|
|
|
begin
|
|
|
|
Result:=SarLongint((Integer(W) shl shift),shift);
|
|
|
|
end;
|
|
|
|
|
|
|
|
procedure TEmit_SOPK.emit_S_MOVK_I32; //sdst.s = signExtend(imm16)
|
|
|
|
Var
|
|
|
|
dst:PsrRegSlot;
|
|
|
|
begin
|
|
|
|
dst:=get_sdst7(FSPI.SOPK.SDST);
|
|
|
|
SetConst_i(dst,dtInt32,SignExtend16(FSPI.SOPK.SIMM));
|
|
|
|
end;
|
|
|
|
|
|
|
|
procedure TEmit_SOPK.emit_S_ADDK_I32; //sdst.s = (sdst.s + signExtend(imm16)); SCC = overflow
|
2022-07-07 10:59:55 +00:00
|
|
|
Var
|
|
|
|
dst:PsrRegSlot;
|
2022-12-06 19:03:06 +00:00
|
|
|
car:PsrRegSlot;
|
|
|
|
src:PsrRegNode;
|
|
|
|
imm:PsrRegNode;
|
2022-07-07 10:59:55 +00:00
|
|
|
begin
|
2022-09-05 13:30:24 +00:00
|
|
|
dst:=get_sdst7(FSPI.SOPK.SDST);
|
2022-12-06 19:03:06 +00:00
|
|
|
car:=get_scc;
|
|
|
|
|
|
|
|
src:=fetch_ssrc8(FSPI.SOPK.SDST,dtInt32);
|
|
|
|
imm:=NewReg_i(dtInt32,SignExtend16(FSPI.SOPK.SIMM));
|
|
|
|
|
|
|
|
OpIAddExt(dst,car,src,imm);
|
2022-07-07 10:59:55 +00:00
|
|
|
end;
|
|
|
|
|
2024-02-28 19:00:07 +00:00
|
|
|
procedure TEmit_SOPK.emit_S_CMPK_I32(OpId:DWORD); //SCC = compareOp(sdst.s, signExtend(imm16.s))
|
|
|
|
Var
|
|
|
|
dst:PsrRegSlot;
|
|
|
|
src:PsrRegNode;
|
|
|
|
imm:PsrRegNode;
|
|
|
|
begin
|
|
|
|
dst:=get_scc;
|
|
|
|
|
|
|
|
src:=fetch_ssrc8(FSPI.SOPK.SDST,dtInt32);
|
|
|
|
imm:=NewReg_i(dtInt32,SignExtend16(FSPI.SOPK.SIMM));
|
|
|
|
|
|
|
|
OpCmpS(OpId,dst,src,imm);
|
|
|
|
end;
|
|
|
|
|
|
|
|
procedure TEmit_SOPK.emit_S_CMPK_U32(OpId:DWORD); //SCC = compareOp(sdst.u, imm16.u)
|
|
|
|
Var
|
|
|
|
dst:PsrRegSlot;
|
|
|
|
src:PsrRegNode;
|
|
|
|
imm:PsrRegNode;
|
|
|
|
begin
|
|
|
|
dst:=get_scc;
|
|
|
|
|
|
|
|
src:=fetch_ssrc8(FSPI.SOPK.SDST,dtUint32);
|
|
|
|
imm:=NewReg_i(dtUint32,FSPI.SOPK.SIMM);
|
|
|
|
|
|
|
|
OpCmpS(OpId,dst,src,imm);
|
|
|
|
end;
|
|
|
|
|
2022-09-05 13:30:24 +00:00
|
|
|
procedure TEmit_SOPK.emit_SOPK;
|
2022-07-07 10:59:55 +00:00
|
|
|
begin
|
|
|
|
|
|
|
|
Case FSPI.SOPK.OP of
|
|
|
|
|
2024-02-28 19:00:07 +00:00
|
|
|
S_CMPK_EQ_I32:emit_S_CMPK_I32(Op.OpIEqual);
|
|
|
|
S_CMPK_LG_I32:emit_S_CMPK_I32(Op.OpINotEqual);
|
|
|
|
S_CMPK_GT_I32:emit_S_CMPK_I32(Op.OpSGreaterThan);
|
|
|
|
S_CMPK_GE_I32:emit_S_CMPK_I32(Op.OpSGreaterThanEqual);
|
|
|
|
S_CMPK_LT_I32:emit_S_CMPK_I32(Op.OpSLessThan);
|
|
|
|
S_CMPK_LE_I32:emit_S_CMPK_I32(Op.OpSLessThanEqual);
|
|
|
|
|
|
|
|
S_CMPK_EQ_U32:emit_S_CMPK_U32(Op.OpIEqual);
|
|
|
|
S_CMPK_LG_U32:emit_S_CMPK_U32(Op.OpINotEqual);
|
|
|
|
S_CMPK_GT_U32:emit_S_CMPK_U32(Op.OpSGreaterThan);
|
|
|
|
S_CMPK_GE_U32:emit_S_CMPK_U32(Op.OpSGreaterThanEqual);
|
|
|
|
S_CMPK_LT_U32:emit_S_CMPK_U32(Op.OpSLessThan);
|
|
|
|
S_CMPK_LE_U32:emit_S_CMPK_U32(Op.OpSLessThanEqual);
|
|
|
|
|
2022-09-05 13:30:24 +00:00
|
|
|
S_MOVK_I32: emit_S_MOVK_I32;
|
2022-07-07 10:59:55 +00:00
|
|
|
|
2022-12-06 19:03:06 +00:00
|
|
|
S_ADDK_I32: emit_S_ADDK_I32;
|
|
|
|
|
2022-07-07 10:59:55 +00:00
|
|
|
else
|
|
|
|
Assert(false,'SOPK?'+IntToStr(FSPI.SOPK.OP));
|
|
|
|
end;
|
|
|
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|
|
|
|
end.
|
|
|
|
|
|
|
|
|