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https://github.com/red-prig/fpPS4.git
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fix OpExtract
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parent
ebfbe572e1
commit
76f2c3947f
@ -317,6 +317,7 @@ begin
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src:=RegsStory.get_ssrc8(SOFFSET);
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Result:=MakeRead(src,rtype);
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end;
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Assert(Result<>nil,'fetch_ssrc8');
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end;
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function TEmitFetch.fetch_ssrc9(SSRC:Word;rtype:TsrDataType):PsrRegNode;
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@ -333,6 +334,7 @@ begin
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src:=RegsStory.get_ssrc9(SSRC);
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Result:=MakeRead(src,rtype);
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end;
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Assert(Result<>nil,'fetch_ssrc9');
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end;
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function TEmitFetch.fetch_ssrc9_pair(SSRC:Word;src:PPsrRegNode;rtype:TsrDataType):Boolean;
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@ -361,6 +363,7 @@ var
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begin
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src:=RegsStory.get_vsrc8(VSRC);
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Result:=MakeRead(src,rtype);
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Assert(Result<>nil,'fetch_vsrc8');
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end;
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function TEmitFetch.fetch_vdst8(VDST:Word;rtype:TsrDataType):PsrRegNode;
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@ -369,6 +372,7 @@ var
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begin
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src:=RegsStory.get_vdst8(VDST);
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Result:=MakeRead(src,rtype);
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Assert(Result<>nil,'fetch_vdst8');
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end;
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procedure TEmitFetch.fetch_vsrc8_vec2h(VSRC:Word;var dst0,dst1:PsrRegNode);
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@ -379,6 +383,7 @@ begin
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pSlot:=RegsStory.get_vsrc8(VSRC);
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dst:=MakeRead(pSlot,dtVec2h);
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Assert(dst<>nil,'fetch_vsrc8_vec2h');
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dst0:=NewReg(dtHalf16);
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dst1:=NewReg(dtHalf16);;
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@ -52,8 +52,15 @@ end;
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procedure TEmit_MUBUF.make_load_comp(dst:PsrRegSlot;dtype:TsrDataType;rsl:PsrRegNode;i:Byte);
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begin
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dst^.New(line,dtype);
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OpExtract(line,dst^.current,rsl,i);
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if rsl^.dtype.isVector then
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begin
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dst^.New(line,dtype);
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OpExtract(line,dst^.current,rsl,i);
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end else
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begin
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Assert(i=0);
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MakeCopy(dst,rsl);
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end;
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end;
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function TEmit_MUBUF.emit_BUFFER_LOAD_VA(src:PPsrRegSlot;count:Byte):Boolean;
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@ -423,6 +423,7 @@ function TEmitOp.OpExtract(pLine:PspirvOp;dst,src:PsrRegNode;id:DWORD):PSpirvOp;
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Var
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node:PSpirvOp;
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begin
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Assert(src^.dtype.isVector);
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node:=AddSpirvOp(pLine,Op.OpCompositeExtract);
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node^.pType:=TypeList.Fetch(dst^.dtype);
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node^.pDst:=dst;
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