mirror of
https://github.com/red-prig/fpPS4.git
synced 2024-11-23 14:29:53 +00:00
392 lines
8.1 KiB
ObjectPascal
392 lines
8.1 KiB
ObjectPascal
unit emit_SOPP;
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{$mode objfpc}{$H+}
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interface
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uses
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sysutils,
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ps4_pssl,
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srType,
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srCFGParser,
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srCFGLabel,
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srCFGCursor,
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srFlow,
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srReg,
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srOp,
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srOpUtils,
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spirv,
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emit_fetch;
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type
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TEmit_SOPP=class(TEmitFetch)
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procedure emit_SOPP;
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procedure emit_S_BRANCH_COND(pSlot:PsrRegSlot;n:Boolean);
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procedure emit_S_BRANCH;
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procedure mark_end_of;
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function IsBegLoop(Adr:TSrcAdr):Boolean;
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function IsEndLoop(Adr:TSrcAdr):Boolean;
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function IsUnknow(Adr:TSrcAdr):Boolean;
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procedure emit_cond_block(pSlot:PsrRegSlot;n:Boolean;adr:TSrcAdr);
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procedure emit_block_unknow(adr:TSrcAdr);
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procedure UpBuildVol(last:PsrOpBlock);
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procedure emit_loop(adr:TSrcAdr);
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procedure emit_loop_cond(pSlot:PsrRegSlot;n:Boolean;adr:TSrcAdr);
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end;
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implementation
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procedure TEmit_SOPP.emit_cond_block(pSlot:PsrRegSlot;n:Boolean;adr:TSrcAdr);
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var
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src:PsrRegNode;
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pOpBlock:PsrOpBlock;
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pOpChild:PsrOpBlock;
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pOpLabel:array[0..1] of PspirvOp;
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pLBlock:PsrCFGBlock;
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Info:array[0..1] of TsrBlockInfo;
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begin
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src:=MakeRead(pSlot,dtBool); //get before OpBranchConditional
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pOpLabel[0]:=NewLabelOp(False);
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pOpLabel[1]:=NewLabelOp(False);
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pLBlock:=Cursor.pCode^.FTop.DownBlock(adr);
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Assert(pLBlock<>@Cursor.pCode^.FTop,'not found');
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Info[0]:=Default(TsrBlockInfo);
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Info[1]:=Default(TsrBlockInfo);
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Case pLBlock^.bType of
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btAdr: //set new adr
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begin
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Info[0].b_adr:=Cursor.Adr;
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Info[0].e_adr:=Cursor.Adr;
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Info[0].bType:=btCond;
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//
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Info[1].b_adr:=pLBlock^.pBLabel^.Adr;
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Info[1].e_adr:=pLBlock^.pELabel^.Adr;
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Info[1].bType:=btAdr;
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end;
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btCond: //normal cond
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begin
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Info[0].b_adr:=pLBlock^.pBLabel^.Adr;
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Info[0].e_adr:=pLBlock^.pELabel^.Adr;
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Info[0].bType:=btCond;
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//
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Info[1].b_adr:=Info[0].b_adr;
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Info[1].e_adr:=Info[0].e_adr;
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Info[1].bType:=btOther;
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end;
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else
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Assert(false,'emit_cond_block');
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end;
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pOpLabel[0]^.Adr:=Info[0].b_adr;
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pOpLabel[1]^.Adr:=Info[0].e_adr;
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pOpBlock:=NewBlockOp(get_snapshot);
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pOpBlock^.SetLabels(pOpLabel[0],pOpLabel[1],nil);
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pOpBlock^.SetInfo(Info[0]);
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pOpBlock^.SetCond(src,not n);
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PushBlockOp(line,pOpBlock,pLBlock);
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OpCondMerge(line,pOpLabel[1]);
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Case n of
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True :OpBranchCond(line,pOpLabel[1],pOpLabel[0],src);
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False:OpBranchCond(line,pOpLabel[0],pOpLabel[1],src);
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end;
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AddSpirvOp(line,pOpLabel[0]);
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//down group
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pOpChild:=AllocBlockOp;
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pOpChild^.SetInfo(Info[1]);
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PushBlockOp(line,pOpChild,nil);
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if (pLBlock^.bType=btAdr) then //set new adr
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begin
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SetPtr(adr.get_pc,btAdr);
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end;
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end;
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procedure TEmit_SOPP.UpBuildVol(last:PsrOpBlock);
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var
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node:PsrOpBlock;
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begin
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node:=Main^.pBlock;
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While (node<>nil) do
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begin
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Case node^.Block.bType of
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btCond:PrivateList.build_volatile_cur(node^.Regs.pSnap_cur);
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btLoop:PrivateList.build_volatile_brk(node^.Regs.pSnap_cur);
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else;
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end;
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if (node=last) then Break;
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node:=node^.Parent;
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end;
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end;
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procedure TEmit_SOPP.emit_loop(adr:TSrcAdr);
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var
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node,pOpBlock:PsrOpBlock;
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pOpLabel:PspirvOp;
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FVolMark:TsrVolMark;
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bnew:Boolean;
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begin
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node:=Main^.pBlock;
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pOpBlock:=node^.FindUpLoop;
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Assert(pOpBlock<>nil,'not found');
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pOpLabel:=nil;
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FVolMark:=vmNone;
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if (pOpBlock^.Block.b_adr.get_pc=adr.get_pc) then //is continue?
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begin
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pOpLabel:=pOpBlock^.Labels.pMrgOp; //-> OpLoopMerge end -> OpLoopMerge before
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pOpBlock^.Cond.FUseCont:=True;
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FVolMark:=vmCont;
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end else
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if (pOpBlock^.Block.b_adr.get_pc=adr.get_pc) then //is break?
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begin
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pOpLabel:=pOpBlock^.Labels.pEndOp;
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FVolMark:=vmBreak;
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end else
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begin
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Assert(false,'emit_loop');
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end;
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Assert(pOpLabel<>nil);
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bnew:=true;
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if Cursor.pBlock^.IsEndOf(Cursor.Adr) then //is last
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begin
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//Assert(node^.Block.e_adr.get_pc=Cursor.Adr.get_pc);
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Case node^.Block.bType of
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btSetpc:;
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else
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begin
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bnew:=false;
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end;
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end;
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end;
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UpBuildVol(pOpBlock);
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node^.Regs.FVolMark:=FVolMark; //mark end of
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OpBranch(line,pOpLabel);
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if bnew then
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begin
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AddSpirvOp(line,NewLabelOp(True));
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end;
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end;
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procedure TEmit_SOPP.emit_loop_cond(pSlot:PsrRegSlot;n:Boolean;adr:TSrcAdr);
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var
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src:PsrRegNode;
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node,pOpBlock:PsrOpBlock;
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pOpLabel:array[0..1] of PspirvOp;
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FVolMark:TsrVolMark;
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begin
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src:=MakeRead(pSlot,dtBool);
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node:=Main^.pBlock;
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pOpBlock:=node^.FindUpLoop;
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Assert(pOpBlock<>nil,'not found');
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pOpLabel[0]:=nil;
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FVolMark:=vmNone;
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if (pOpBlock^.Block.b_adr.get_pc=adr.get_pc) then //is continue?
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begin
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pOpLabel[0]:=pOpBlock^.Labels.pMrgOp; //-> OpLoopMerge end -> OpLoopMerge before
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pOpBlock^.Cond.FUseCont:=True;
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FVolMark:=vmCont;
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end else
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if (pOpBlock^.Block.b_adr.get_pc=adr.get_pc) then //is break?
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begin
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pOpLabel[0]:=pOpBlock^.Labels.pEndOp;
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FVolMark:=vmBreak;
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end else
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begin
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Assert(false,'emit_loop');
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end;
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Assert(pOpLabel[0]<>nil);
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pOpLabel[1]:=NewLabelOp(False);
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UpBuildVol(pOpBlock);
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node^.Regs.FVolMark:=FVolMark; //mark end of
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OpCondMerge(line,pOpLabel[1]);
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Case n of
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True :OpBranchCond(line,pOpLabel[0],pOpLabel[1],src);
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False:OpBranchCond(line,pOpLabel[1],pOpLabel[0],src);
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end;
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AddSpirvOp(line,pOpLabel[1]);
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end;
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function TEmit_SOPP.IsBegLoop(Adr:TSrcAdr):Boolean;
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var
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node:PsrCFGBlock;
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begin
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Result:=false;
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node:=Cursor.pBlock^.FindUpLoop;
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if (node<>nil) then
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begin
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Result:=node^.pBLabel^.Adr.get_pc=Adr.get_pc;
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end;
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end;
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function TEmit_SOPP.IsEndLoop(Adr:TSrcAdr):Boolean;
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var
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node:PsrCFGBlock;
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begin
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Result:=false;
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node:=Cursor.pBlock^.FindUpLoop;
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if (node<>nil) then
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begin
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Result:=node^.pELabel^.Adr.get_pc=Adr.get_pc;
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end;
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end;
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function TEmit_SOPP.IsUnknow(Adr:TSrcAdr):Boolean;
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var
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pLabel:PsrLabel;
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begin
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pLabel:=FindLabel(Adr);
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Assert(pLabel<>nil);
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Result:=pLabel^.IsType(ltUnknow);
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end;
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procedure TEmit_SOPP.emit_S_BRANCH_COND(pSlot:PsrRegSlot;n:Boolean);
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var
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c_adr,b_adr:TSrcAdr;
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pLabel:PsrLabel;
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begin
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c_adr:=Cursor.Adr;
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b_adr:=c_adr;
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b_adr.Offdw:=get_branch_offset(FSPI);
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pLabel:=FindLabel(b_adr);
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Assert(pLabel<>nil);
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//Assert(not pLabel^.IsType(ltUnknow));
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if pLabel^.IsType(ltBegAdr) then //adr
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begin
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emit_cond_block(pSlot,n,b_adr);
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end else
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if (SmallInt(FSPI.SOPP.SIMM)<0) then //up
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begin //continue?
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if not IsBegLoop(b_adr) then Assert(false,'Unknow');
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emit_loop_cond(pSlot,n,b_adr);
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end else
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begin //down
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if Cursor.pBlock^.IsBigOf(b_adr) then
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begin //break?
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if not IsEndLoop(b_adr) then Assert(false,'Unknow');
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emit_loop_cond(pSlot,n,b_adr);
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end else
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begin //cond
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emit_cond_block(pSlot,n,c_adr);
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end;
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end;
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end;
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procedure TEmit_SOPP.emit_block_unknow(adr:TSrcAdr);
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var
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c_adr:TSrcAdr;
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e_adr:TSrcAdr;
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pOpChild:PsrOpBlock;
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Info:TsrBlockInfo;
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begin
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Info:=Default(TsrBlockInfo);
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c_adr:=Cursor.Adr; //get current
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SetPtr(adr.get_pc,btAdrBranch); //set new
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e_adr:=Cursor.pCode^.FTop.pELabel^.Adr; //get end of code
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SetPtr(c_adr.get_pc,btMain); //ret current
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Info.b_adr:=adr;
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Info.e_adr:=e_adr;
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Info.bType:=btAdrBranch;
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//down group
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pOpChild:=AllocBlockOp;
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pOpChild^.SetInfo(Info);
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PushBlockOp(line,pOpChild,nil);
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SetPtr(adr.get_pc,btAdrBranch);
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end;
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procedure TEmit_SOPP.emit_S_BRANCH;
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var
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c_adr,b_adr:TSrcAdr;
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begin
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c_adr:=Cursor.Adr;
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b_adr:=c_adr;
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b_adr.Offdw:=get_branch_offset(FSPI);
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if IsUnknow(b_adr) then
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begin
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emit_block_unknow(b_adr);
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end else
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if (SmallInt(FSPI.SOPP.SIMM)<0) then //up
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begin //continue?
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if not IsBegLoop(b_adr) then Assert(false,'Unknow');
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emit_loop(b_adr);
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end else //down
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begin //break?
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if not IsEndLoop(b_adr) then Assert(false,'Unknow');
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emit_loop(b_adr);
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end;
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end;
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procedure TEmit_SOPP.mark_end_of;
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begin
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Main^.pBlock^.Regs.FVolMark:=vmEnd; //mark end of
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end;
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procedure TEmit_SOPP.emit_SOPP;
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begin
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Case FSPI.SOPP.OP of
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S_NOP,
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S_WAITCNT:;
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S_TTRACEDATA:; //write_thread_trace_data(M0[31:0])
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S_ENDPGM:
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begin
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if not is_term_op(line) then
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begin
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AddSpirvOp(Op.OpReturn);
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end;
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mark_end_of;
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end;
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S_CBRANCH_SCC0 :emit_S_BRANCH_COND(get_scc ,false);
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S_CBRANCH_SCC1 :emit_S_BRANCH_COND(get_scc ,true);
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S_CBRANCH_VCCZ :emit_S_BRANCH_COND(get_vcc0 ,false);
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S_CBRANCH_VCCNZ :emit_S_BRANCH_COND(get_vcc0 ,true);
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S_CBRANCH_EXECZ :emit_S_BRANCH_COND(get_exec0,false);
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S_CBRANCH_EXECNZ:emit_S_BRANCH_COND(get_exec0,true);
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S_BRANCH :emit_S_BRANCH;
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else
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Assert(false,'SOPP?'+IntToStr(FSPI.SOPP.OP));
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end;
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end;
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end.
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