mirror of
https://github.com/red-prig/fpPS4.git
synced 2024-11-23 14:29:53 +00:00
678 lines
19 KiB
ObjectPascal
678 lines
19 KiB
ObjectPascal
{$mode objfpc}{$H+}
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Uses
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classes,
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Sysutils,
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si_ci_vi_merged_offset,
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si_ci_vi_merged_registers,
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ps4_pssl,
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ps4_shader,
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srConfig,
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SprvEmit,
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emit_post,
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emit_alloc,
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emit_print,
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emit_bin;
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var
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cfg:record
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FName:RawByteString;
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FSave:RawByteString;
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FPrintInfo:Boolean;
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FPrintSpv:Boolean;
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//
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cfg:TsrConfig;
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end;
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type
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TDUMP_WORD=packed record
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REG,COUNT:WORD;
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end;
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procedure SaveToFile_Spv(const FName:RawByteString;var SprvEmit:TSprvEmit);
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var
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F:TFileStream;
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begin
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F:=TFileStream.Create(FName,fmCreate);
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SprvEmit.SaveToStream(F);
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F.Free;
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end;
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type
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TSPI_USER_DATA=array[0..15] of DWORD;
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var
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GPU_REGS:packed record
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PS:packed record
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Addr:Pointer;
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INPUT_CNTL:array[0..31] of TSPI_PS_INPUT_CNTL_0;
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RSRC1:TSPI_SHADER_PGM_RSRC1_PS;
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RSRC2:TSPI_SHADER_PGM_RSRC2_PS;
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RSRC3:TSPI_SHADER_PGM_RSRC3_PS;
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Z_FORMAT :TSPI_SHADER_Z_FORMAT;
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COL_FORMAT:TSPI_SHADER_COL_FORMAT;
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INPUT_ENA :TSPI_PS_INPUT_ENA;
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INPUT_ADDR:TSPI_PS_INPUT_ADDR;
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IN_CONTROL:TSPI_PS_IN_CONTROL;
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BARYC_CNTL:TSPI_BARYC_CNTL;
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SHADER_CONTROL:TDB_SHADER_CONTROL;
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SHADER_MASK:TCB_SHADER_MASK;
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USER_DATA:TSPI_USER_DATA;
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end;
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VS:packed record
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Addr:Pointer;
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RSRC1:TSPI_SHADER_PGM_RSRC1_VS;
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RSRC2:TSPI_SHADER_PGM_RSRC2_VS;
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RSRC3:TSPI_SHADER_PGM_RSRC3_VS;
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OUT_CONFIG:TSPI_VS_OUT_CONFIG;
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POS_FORMAT:TSPI_SHADER_POS_FORMAT;
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OUT_CNTL :TPA_CL_VS_OUT_CNTL;
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USER_DATA:TSPI_USER_DATA;
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end;
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CS:packed record
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Addr:Pointer;
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RSRC1:TCOMPUTE_PGM_RSRC1;
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RSRC2:TCOMPUTE_PGM_RSRC2;
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STATIC_THREAD_MGMT_SE0:TCOMPUTE_STATIC_THREAD_MGMT_SE0;
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STATIC_THREAD_MGMT_SE1:TCOMPUTE_STATIC_THREAD_MGMT_SE1;
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RESOURCE_LIMITS:TCOMPUTE_RESOURCE_LIMITS;
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NUM_THREAD_X:TCOMPUTE_NUM_THREAD_X;
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NUM_THREAD_Y:TCOMPUTE_NUM_THREAD_Y;
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NUM_THREAD_Z:TCOMPUTE_NUM_THREAD_Z;
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USER_DATA:TSPI_USER_DATA;
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end;
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VGT_NUM_INSTANCES:TVGT_NUM_INSTANCES;
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end;
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Blocks:TFPList;
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procedure ClearBlocks;
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var
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i:Integer;
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begin
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if (Blocks=nil) then
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begin
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Blocks:=TFPList.Create;
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Exit;
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end;
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if (Blocks.Count<>0) then
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For i:=0 to Blocks.Count-1 do
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begin
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FreeMem(Blocks.Items[i]);
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end;
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Blocks.Clear;
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end;
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procedure _print_hex(addr:Pointer;size:DWORD);
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var
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i:DWORD;
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begin
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For i:=0 to size-1 do
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begin
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if (i<>0) and ((i mod 16)=0) then Writeln;
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Write(HexStr(PByte(addr)[i],2));
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end;
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if (i<>0) and ((i mod 16)<>0) then Writeln;
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end;
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procedure load_dump(const fname:RawByteString);
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var
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M:TMemoryStream;
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W:TDUMP_WORD;
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V:DWORD;
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addr:Pointer;
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size,i:DWORD;
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begin
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ClearBlocks;
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FillChar(GPU_REGS,SizeOf(GPU_REGS),0);
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M:=TMemoryStream.Create;
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M.LoadFromFile(fname);
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M.Position:=0;
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V:=0;
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W:=Default(TDUMP_WORD);
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repeat
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if M.Read(W,SizeOf(W))<>SizeOf(W) then Break;
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if (W.COUNT=0) then //simple
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begin
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if M.Read(V,SizeOf(V))<>SizeOf(V) then Break;
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Case W.REG of
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mmCOMPUTE_PGM_RSRC1 :DWORD(GPU_REGS.CS.RSRC1 ):=V;
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mmCOMPUTE_PGM_RSRC2 :DWORD(GPU_REGS.CS.RSRC2 ):=V;
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mmCOMPUTE_NUM_THREAD_X:DWORD(GPU_REGS.CS.NUM_THREAD_X):=V;
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mmCOMPUTE_NUM_THREAD_Y:DWORD(GPU_REGS.CS.NUM_THREAD_Y):=V;
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mmCOMPUTE_NUM_THREAD_Z:DWORD(GPU_REGS.CS.NUM_THREAD_Z):=V;
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//
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mmCOMPUTE_USER_DATA_0..mmCOMPUTE_USER_DATA_15:
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begin
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i:=W.REG-mmCOMPUTE_USER_DATA_0;
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GPU_REGS.CS.USER_DATA[i]:=V;
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end;
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//
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mmCOMPUTE_STATIC_THREAD_MGMT_SE0:DWORD(GPU_REGS.CS.STATIC_THREAD_MGMT_SE0):=V;
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mmCOMPUTE_STATIC_THREAD_MGMT_SE1:DWORD(GPU_REGS.CS.STATIC_THREAD_MGMT_SE1):=V;
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mmCOMPUTE_RESOURCE_LIMITS :DWORD(GPU_REGS.CS.RESOURCE_LIMITS ):=V;
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//
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mmSPI_SHADER_PGM_RSRC1_PS:DWORD(GPU_REGS.PS.RSRC1 ):=V;
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mmSPI_SHADER_PGM_RSRC2_PS:DWORD(GPU_REGS.PS.RSRC2 ):=V;
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mmSPI_SHADER_PGM_RSRC3_PS:DWORD(GPU_REGS.PS.RSRC3 ):=V;
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mmSPI_SHADER_Z_FORMAT :DWORD(GPU_REGS.PS.Z_FORMAT ):=V;
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mmSPI_SHADER_COL_FORMAT :DWORD(GPU_REGS.PS.COL_FORMAT ):=V;
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mmSPI_PS_INPUT_ENA :DWORD(GPU_REGS.PS.INPUT_ENA ):=V;
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mmSPI_PS_INPUT_ADDR :DWORD(GPU_REGS.PS.INPUT_ADDR ):=V;
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mmSPI_PS_IN_CONTROL :DWORD(GPU_REGS.PS.IN_CONTROL ):=V;
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mmSPI_BARYC_CNTL :DWORD(GPU_REGS.PS.BARYC_CNTL ):=V;
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mmDB_SHADER_CONTROL :DWORD(GPU_REGS.PS.SHADER_CONTROL):=V;
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mmCB_SHADER_MASK :DWORD(GPU_REGS.PS.SHADER_MASK ):=V;
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//
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mmSPI_SHADER_USER_DATA_PS_0..mmSPI_SHADER_USER_DATA_PS_15:
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begin
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i:=W.REG-mmSPI_SHADER_USER_DATA_PS_0;
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GPU_REGS.PS.USER_DATA[i]:=V;
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end;
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//
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mmSPI_PS_INPUT_CNTL_0..mmSPI_PS_INPUT_CNTL_31:
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begin
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i:=W.REG-mmSPI_PS_INPUT_CNTL_0;
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DWORD(GPU_REGS.PS.INPUT_CNTL[i]):=V;
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end;
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//
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mmSPI_SHADER_PGM_RSRC1_VS:DWORD(GPU_REGS.VS.RSRC1 ):=V;
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mmSPI_SHADER_PGM_RSRC2_VS:DWORD(GPU_REGS.VS.RSRC2 ):=V;
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mmSPI_SHADER_PGM_RSRC3_VS:DWORD(GPU_REGS.VS.RSRC3 ):=V;
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mmSPI_VS_OUT_CONFIG :DWORD(GPU_REGS.VS.OUT_CONFIG):=V;
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mmSPI_SHADER_POS_FORMAT :DWORD(GPU_REGS.VS.POS_FORMAT):=V;
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mmPA_CL_VS_OUT_CNTL :DWORD(GPU_REGS.VS.OUT_CNTL ):=V;
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//
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mmSPI_SHADER_USER_DATA_VS_0..mmSPI_SHADER_USER_DATA_VS_15:
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begin
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i:=W.REG-mmSPI_SHADER_USER_DATA_VS_0;
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GPU_REGS.VS.USER_DATA[i]:=V;
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end;
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//
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mmVGT_NUM_INSTANCES :DWORD(GPU_REGS.VGT_NUM_INSTANCES):=V;
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end;
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end else
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begin
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size:=(W.COUNT+1)*4;
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if cfg.FPrintInfo then
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if (W.COUNT<>0) then Writeln('block:',getRegName(W.REG),' size:',size);
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addr:=AllocMem(size+7);
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if M.Read(Align(addr,8)^,size)<>size then
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begin
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FreeMem(addr);
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Break;
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end else
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begin
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Blocks.Add(addr);
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addr:=Align(addr,8);
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end;
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//_print_hex(addr,size);
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Case W.REG of
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mmCOMPUTE_PGM_LO:
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begin
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GPU_REGS.CS.Addr:=addr;
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end;
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mmSPI_SHADER_PGM_LO_PS:
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begin
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GPU_REGS.PS.Addr:=addr;
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end;
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mmSPI_SHADER_PGM_LO_VS:
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begin
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GPU_REGS.VS.Addr:=addr;
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end;
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mmCOMPUTE_USER_DATA_0..mmCOMPUTE_USER_DATA_14:
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begin
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i:=W.REG-mmCOMPUTE_USER_DATA_0;
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GPU_REGS.CS.USER_DATA[i+0]:=DWORD({%H-}QWORD(addr));
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GPU_REGS.CS.USER_DATA[i+1]:=DWORD({%H-}QWORD(addr) shr 32);
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end;
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mmSPI_SHADER_USER_DATA_PS_0..mmSPI_SHADER_USER_DATA_PS_14:
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begin
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i:=W.REG-mmSPI_SHADER_USER_DATA_PS_0;
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GPU_REGS.PS.USER_DATA[i+0]:=DWORD({%H-}QWORD(addr));
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GPU_REGS.PS.USER_DATA[i+1]:=DWORD({%H-}QWORD(addr) shr 32);
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end;
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mmSPI_SHADER_USER_DATA_VS_0..mmSPI_SHADER_USER_DATA_VS_14:
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begin
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i:=W.REG-mmSPI_SHADER_USER_DATA_VS_0;
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GPU_REGS.VS.USER_DATA[i+0]:=DWORD({%H-}QWORD(addr));
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GPU_REGS.VS.USER_DATA[i+1]:=DWORD({%H-}QWORD(addr) shr 32);
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end;
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end;
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end;
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until false;
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end;
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procedure load_pssl(base:Pointer);
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var
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info:PShaderBinaryInfo;
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Slots:PInputUsageSlot;
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SprvEmit:TSprvEmit;
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i:Byte;
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begin
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if (base=nil) then Exit;
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info:=_calc_shader_info(base,MemSize(base) div 4);
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if cfg.FPrintInfo then
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if (info<>nil) then
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begin
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Writeln('signature =',info^.signature );
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Writeln('version =',info^.version );
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Writeln('pssl_or_cg =',info^.pssl_or_cg );
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Writeln('cached =',info^.cached );
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Writeln('m_type =',info^.m_type );
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Writeln('source_type =',info^.source_type );
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Writeln('length =',info^.length );
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Writeln('chunkUsageBaseOffsetInDW=',info^.chunkUsageBaseOffsetInDW);
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Writeln('numInputUsageSlots =',info^.numInputUsageSlots );
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Writeln('isSrt =',info^.isSrt );
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Writeln('isSrtUsedInfoValid =',info^.isSrtUsedInfoValid );
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Writeln('isExtendedUsageInfo =',info^.isExtendedUsageInfo );
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Writeln('reserved2 =',info^.reserved2 );
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Writeln('reserved3 =',info^.reserved3 );
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Writeln('shaderHash0 =','0x',HexStr(info^.shaderHash0,8));
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Writeln('shaderHash1 =','0x',HexStr(info^.shaderHash1,8));
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Writeln('crc32 =','0x',HexStr(info^.crc32,8) );
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writeln;
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if (info^.numInputUsageSlots<>0) then
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begin
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Slots:=_calc_shader_slot(info);
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For i:=0 to info^.numInputUsageSlots-1 do
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begin
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Writeln('Slot[',i,']');
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case Slots[i].m_usageType of
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kShaderInputUsageImmResource :Writeln(' ImmResource ');
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kShaderInputUsageImmSampler :Writeln(' ImmSampler ');
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kShaderInputUsageImmConstBuffer :Writeln(' ImmConstBuffer ');
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kShaderInputUsageImmVertexBuffer :Writeln(' ImmVertexBuffer ');
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kShaderInputUsageImmRwResource :Writeln(' ImmRwResource ');
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kShaderInputUsageImmAluFloatConst :Writeln(' ImmAluFloatConst ');
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kShaderInputUsageImmAluBool32Const :Writeln(' ImmAluBool32Const ');
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kShaderInputUsageImmGdsCounterRange :Writeln(' ImmGdsCounterRange ');
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kShaderInputUsageImmGdsMemoryRange :Writeln(' ImmGdsMemoryRange ');
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kShaderInputUsageImmGwsBase :Writeln(' ImmGwsBase ');
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kShaderInputUsageImmShaderResourceTable :Writeln(' ImmShaderResourceTable ');
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kShaderInputUsageImmLdsEsGsSize :Writeln(' ImmLdsEsGsSize ');
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kShaderInputUsageSubPtrFetchShader :Writeln(' SubPtrFetchShader ');
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kShaderInputUsagePtrResourceTable :Writeln(' PtrResourceTable ');
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kShaderInputUsagePtrInternalResourceTable :Writeln(' PtrInternalResourceTable ');
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kShaderInputUsagePtrSamplerTable :Writeln(' PtrSamplerTable ');
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kShaderInputUsagePtrConstBufferTable :Writeln(' PtrConstBufferTable ');
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kShaderInputUsagePtrVertexBufferTable :Writeln(' PtrVertexBufferTable ');
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kShaderInputUsagePtrSoBufferTable :Writeln(' PtrSoBufferTable ');
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kShaderInputUsagePtrRwResourceTable :Writeln(' PtrRwResourceTable ');
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kShaderInputUsagePtrInternalGlobalTable :Writeln(' PtrInternalGlobalTable ');
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kShaderInputUsagePtrExtendedUserData :Writeln(' PtrExtendedUserData ');
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kShaderInputUsagePtrIndirectResourceTable :Writeln(' PtrIndirectResourceTable ');
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kShaderInputUsagePtrIndirectInternalResourceTable:Writeln(' PtrIndirectInternalResourceTable');
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kShaderInputUsagePtrIndirectRwResourceTable :Writeln(' PtrIndirectRwResourceTable ');
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kShaderInputUsageImmGdsKickRingBufferOffse :Writeln(' ImmGdsKickRingBufferOffse ');
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kShaderInputUsageImmVertexRingBufferOffse :Writeln(' ImmVertexRingBufferOffse ');
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kShaderInputUsagePtrDispatchDraw :Writeln(' PtrDispatchDraw ');
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kShaderInputUsageImmDispatchDrawInstances :Writeln(' ImmDispatchDrawInstances ');
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else
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Writeln(' m_usageType=',Slots[i].m_usageType);
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end;
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Writeln(' apiSlot=',Slots[i].m_apiSlot);
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Writeln(' startRegister=',Slots[i].m_startRegister);
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Writeln(' param=',HexStr(Slots[i].m_srtSizeInDWordMinusOne,2));
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end;
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Writeln;
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end;
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end;
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Assert(info<>nil);
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SprvEmit:=TSprvEmit.Create;
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case info^.m_type of
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kShaderTypePs :
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begin
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if cfg.FPrintInfo then
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Writeln('USGPR:',GPU_REGS.PS.RSRC2.USER_SGPR,' VGPRS:',GPU_REGS.PS.RSRC1.VGPRS,' SGPRS:',GPU_REGS.PS.RSRC1.SGPRS);
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SprvEmit.InitPs(GPU_REGS.PS.RSRC1,GPU_REGS.PS.RSRC2,GPU_REGS.PS.INPUT_ENA);
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SprvEmit.SetUserData(@GPU_REGS.PS.USER_DATA);
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end;
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kShaderTypeVsVs:
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begin
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if cfg.FPrintInfo then
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Writeln('USGPR:',GPU_REGS.VS.RSRC2.USER_SGPR,' VGPRS:',GPU_REGS.VS.RSRC1.VGPRS,' SGPRS:',GPU_REGS.VS.RSRC1.SGPRS);
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SprvEmit.InitVs(GPU_REGS.VS.RSRC1,GPU_REGS.VS.RSRC2,GPU_REGS.VGT_NUM_INSTANCES);
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SprvEmit.SetUserData(@GPU_REGS.VS.USER_DATA);
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end;
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kShaderTypeCs:
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begin
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if cfg.FPrintInfo then
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Writeln('USGPR:',GPU_REGS.CS.RSRC2.USER_SGPR,' VGPRS:',GPU_REGS.CS.RSRC1.VGPRS,' SGPRS:',GPU_REGS.CS.RSRC1.SGPRS);
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SprvEmit.InitCs(GPU_REGS.CS.RSRC1,GPU_REGS.CS.RSRC2,GPU_REGS.CS.NUM_THREAD_X,GPU_REGS.CS.NUM_THREAD_Y,GPU_REGS.CS.NUM_THREAD_Z);
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SprvEmit.SetUserData(@GPU_REGS.CS.USER_DATA);
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end;
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else
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begin
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_parse_print(base);
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Exit;
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end;
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end;
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SprvEmit.Config:=cfg.cfg;
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if (SprvEmit.ParseStage(base)>1) then
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begin
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Writeln(StdErr,'Shader Parse Err');
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end;
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if cfg.cfg.PrintAsm or cfg.FPrintSpv or (cfg.FSave<>'') then
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begin
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SprvEmit.PostStage;
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SprvEmit.AllocStage;
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end;
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if cfg.FPrintSpv then
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begin
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SprvEmit.Print;
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Writeln;
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end;
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if (cfg.FSave<>'') then
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begin
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SaveToFile_Spv(cfg.FSave,SprvEmit);
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end;
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if cfg.FPrintInfo then
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Writeln('used_size=',SprvEmit.Allocator.used_size);
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SprvEmit.Free;
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end;
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function ParseCmd:Boolean;
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var
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i,n:Integer;
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label
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promo;
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begin
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if (ParamCount=0) then
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begin
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promo:
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Exit(False);
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end;
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cfg.FName:='';
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cfg.FSave:='';
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cfg.FPrintInfo:=False;
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cfg.FPrintSpv :=False;
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cfg.cfg.Init;
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n:=-1;
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For i:=1 to ParamCount do
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begin
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case LowerCase(ParamStr(i)) of
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'-i':cfg.FPrintInfo:=True;
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'-a':cfg.cfg.PrintAsm:=True;
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'-p':cfg.FPrintSpv:=True;
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'-eva':cfg.cfg.UseVertexInput:=True;
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'-dva':cfg.cfg.UseVertexInput:=False;
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'-etb':cfg.cfg.UseTexelBuffer:=True;
|
|
'-dtb':cfg.cfg.UseTexelBuffer:=False;
|
|
|
|
'-eoh':cfg.cfg.UseOutput16:=True;
|
|
'-doh':cfg.cfg.UseOutput16:=False;
|
|
|
|
'-b':n:=0;
|
|
|
|
'-mubo':n:=1;//maxUniformBufferRange
|
|
'-pco':n:=2;//PushConstantsOffset
|
|
'-pcs':n:=3;//maxPushConstantsSize
|
|
'-sboa':n:=4;//minStorageBufferOffsetAlignment
|
|
'-uboa':n:=5;//minUniformBufferOffsetAlignment
|
|
|
|
else
|
|
begin
|
|
Case n of
|
|
-1:cfg.FName:=ParamStr(i);
|
|
0:cfg.FSave:=ParamStr(i);
|
|
1:cfg.cfg.maxUniformBufferRange :=StrToInt64Def(ParamStr(i),0);
|
|
2:cfg.cfg.PushConstantsOffset :=StrToInt64Def(ParamStr(i),0);
|
|
3:cfg.cfg.maxPushConstantsSize :=StrToInt64Def(ParamStr(i),0);
|
|
4:cfg.cfg.minStorageBufferOffsetAlignment:=StrToInt64Def(ParamStr(i),0);
|
|
5:cfg.cfg.minUniformBufferOffsetAlignment:=StrToInt64Def(ParamStr(i),0);
|
|
end;
|
|
n:=-1;
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
Result:=True;
|
|
end;
|
|
|
|
begin
|
|
DefaultSystemCodePage:=CP_UTF8;
|
|
DefaultUnicodeCodePage:=CP_UTF8;
|
|
DefaultFileSystemCodePage:=CP_UTF8;
|
|
DefaultRTLFileSystemCodePage:=CP_UTF8;
|
|
UTF8CompareLocale:=CP_UTF8;
|
|
|
|
FillChar(cfg,SizeOf(cfg),0);
|
|
|
|
ParseCmd;
|
|
|
|
if (cfg.FName='') then
|
|
begin
|
|
//
|
|
end;
|
|
|
|
|
|
if (cfg.FName<>'') then
|
|
begin
|
|
load_dump(cfg.FName);
|
|
end;
|
|
|
|
load_pssl(GPU_REGS.CS.Addr);
|
|
|
|
load_pssl(GPU_REGS.VS.Addr);
|
|
load_pssl(GPU_REGS.PS.Addr);
|
|
|
|
if cfg.FPrintInfo then
|
|
begin
|
|
readln;
|
|
end;
|
|
end.
|
|
|
|
{
|
|
|
|
///////////////////source ext
|
|
|
|
[USER_DATA]
|
|
|
|
|
v
|
|
//DATA LAYOUT
|
|
[PARENT_LAYOUT|DATA_TYPE|OFFSET|INDEX]
|
|
^ ^ ^
|
|
| | | //CHILD LAYOUT //UNIFORM
|
|
| |[PARENT_LAYOUT|DATA_TYPE|OFFSET] <- [SOURCE_LAYOUT|HANDLE_TYPE|PVAR|PREG]
|
|
| | ^ ^
|
|
| | | |
|
|
| | /-------------------------/ |
|
|
| | | |
|
|
| | v |
|
|
| | [PVAR] <- [opLoad]<--------------/
|
|
| |
|
|
| | //CHILD LAYOUT //BUFFER
|
|
| [PARENT_LAYOUT|DATA_TYPE|OFFSET] <- [SOURCE_LAYOUT|CAST_NUM|PVAR] <-> [PVAR]<----------\
|
|
| ^ |
|
|
| | //BUFFER FIELD |
|
|
| [SOURCE_BUFFER|SOURCE_FIELD|ID|OFFSET|SIZE|PREG] |
|
|
| ^ | |
|
|
| /------------/ | |
|
|
| | | |
|
|
| [OpAccessChain|ID|ID...]<-------------------------/
|
|
| ^ |
|
|
| | |
|
|
| [opLoad]<-----------------------------------/
|
|
|
|
|
|[SET]
|
|
|
|
|
| //CHAIN LAYOUT
|
|
[SOURCE_LAYOUT|OFFSET|PREG] <-> [opLoad]
|
|
|
|
///////////////////
|
|
|
|
|
|
[FUserDataVar]
|
|
^
|
|
| /----------------------------------------v---------------------------\
|
|
[pArray|Source] <- [OpAccessChain|[Index]] <- [PChain|pWriter|ID] <- [opLoad] <- [pReg|ID]
|
|
|
|
|
|
[PChain]*x
|
|
^ ^
|
|
| |
|
|
[pGroup|chains]
|
|
|
|
//////////////////
|
|
|
|
[pUniform]
|
|
| ^
|
|
v /-----------------------\
|
|
[Forked_Var] <- [opLoad] <- [pReg|ID] <- [OpImageRead1D]
|
|
|
|
//////////////////
|
|
|
|
[OpVariable] [pointer struct] PushConstant
|
|
^ ^
|
|
| |
|
|
| [OpTypePointer] PushConstant [struct]
|
|
| ^
|
|
| |
|
|
| [OpTypeStruct] [item1:type] <- aType
|
|
| ^ ^ ^
|
|
| | | |
|
|
| | [OpMemberDecorate] [struct] [item1:index] Offset 0
|
|
| |
|
|
| [OpDecorate] [struct] Block
|
|
|
|
|
| [OpTypePointer] PushConstant [item1:type]
|
|
| |
|
|
| v
|
|
[OpAccessChain] [pointer type] [pVar] [item1:index]
|
|
|
|
}
|
|
|
|
|
|
{
|
|
|
|
x:=1 //write
|
|
|
|
[opLabel]->
|
|
|
|
y:=x+1 //read ^make var
|
|
|
|
[opLabel]<-
|
|
|
|
//////////////////////////////
|
|
|
|
y:=0 //write
|
|
|
|
[opLabel]->
|
|
|
|
y:=1 //write
|
|
|
|
y:=y+y //write <-
|
|
|
|
[opLabel]<-
|
|
|
|
x:=y+1; //read ^make var
|
|
|
|
y:=1 //write <- reset var
|
|
|
|
//////////////////////////////
|
|
|
|
y:=0 //write
|
|
|
|
[opLabel]->
|
|
|
|
x:=1 //write
|
|
|
|
[opLabel]<-
|
|
|
|
x:=y+1; //read ^nop
|
|
|
|
//////////////////////////////
|
|
|
|
[OpCond]
|
|
|
|
IF[ [OpSelectionMerge] [OpBranchConditional] [OpLabel]
|
|
|
|
//body
|
|
|
|
[OpLabel] ]ENDIF
|
|
|
|
//////////////////////////////
|
|
|
|
IF[ [OpBranch] [OpLabel]
|
|
|
|
WHILE[ [OpLoopMerge] [OpBranch] [OpLabel]
|
|
|
|
//body
|
|
|
|
[OpBranch] [OpLabel] ]WHILE(1)
|
|
|
|
[OpCond]
|
|
|
|
[OpBranchConditional] [OpLabel] ]WHILE(2) ]ENDIF
|
|
|
|
//////////////////////////////
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|