2022-12-30 19:36:32 +00:00
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/*
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* RISC-V Disassembler
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*
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* Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com>
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef RISCV_DISASSEMBLER_H
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#define RISCV_DISASSEMBLER_H
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#include <cstdint>
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/* types */
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typedef uint64_t rv_inst;
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typedef uint16_t rv_opcode;
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/* enums */
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typedef enum {
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rv32,
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rv64,
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rv128
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} rv_isa;
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typedef enum {
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rv_rm_rne = 0,
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rv_rm_rtz = 1,
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rv_rm_rdn = 2,
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rv_rm_rup = 3,
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rv_rm_rmm = 4,
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rv_rm_dyn = 7,
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} rv_rm;
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typedef enum {
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rv_fence_i = 8,
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rv_fence_o = 4,
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rv_fence_r = 2,
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rv_fence_w = 1,
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} rv_fence;
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typedef enum {
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rv_ireg_zero,
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rv_ireg_ra,
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rv_ireg_sp,
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rv_ireg_gp,
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rv_ireg_tp,
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rv_ireg_t0,
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rv_ireg_t1,
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rv_ireg_t2,
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rv_ireg_s0,
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rv_ireg_s1,
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rv_ireg_a0,
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rv_ireg_a1,
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rv_ireg_a2,
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rv_ireg_a3,
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rv_ireg_a4,
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rv_ireg_a5,
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rv_ireg_a6,
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rv_ireg_a7,
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rv_ireg_s2,
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rv_ireg_s3,
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rv_ireg_s4,
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rv_ireg_s5,
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rv_ireg_s6,
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rv_ireg_s7,
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rv_ireg_s8,
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rv_ireg_s9,
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rv_ireg_s10,
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rv_ireg_s11,
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rv_ireg_t3,
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rv_ireg_t4,
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rv_ireg_t5,
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rv_ireg_t6,
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} rv_ireg;
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typedef enum {
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rvc_end,
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rvc_rd_eq_ra,
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rvc_rd_eq_x0,
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rvc_rs1_eq_x0,
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rvc_rs2_eq_x0,
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rvc_rs2_eq_rs1,
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rvc_rs1_eq_ra,
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rvc_imm_eq_zero,
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rvc_imm_eq_n1,
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rvc_imm_eq_p1,
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rvc_csr_eq_0x001,
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rvc_csr_eq_0x002,
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rvc_csr_eq_0x003,
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rvc_csr_eq_0xc00,
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rvc_csr_eq_0xc01,
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rvc_csr_eq_0xc02,
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rvc_csr_eq_0xc80,
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rvc_csr_eq_0xc81,
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rvc_csr_eq_0xc82,
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} rvc_constraint;
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typedef enum {
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rv_codec_illegal,
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rv_codec_none,
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rv_codec_u,
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rv_codec_uj,
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rv_codec_i,
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rv_codec_i_sh5,
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rv_codec_i_sh6,
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rv_codec_i_sh7,
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rv_codec_i_csr,
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rv_codec_s,
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rv_codec_sb,
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rv_codec_r,
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rv_codec_r_m,
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rv_codec_r4_m,
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rv_codec_r_a,
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rv_codec_r_l,
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rv_codec_r_f,
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rv_codec_cb,
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rv_codec_cb_imm,
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rv_codec_cb_sh5,
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rv_codec_cb_sh6,
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rv_codec_ci,
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rv_codec_ci_sh5,
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rv_codec_ci_sh6,
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rv_codec_ci_16sp,
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rv_codec_ci_lwsp,
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rv_codec_ci_ldsp,
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rv_codec_ci_lqsp,
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rv_codec_ci_li,
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rv_codec_ci_lui,
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rv_codec_ci_none,
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rv_codec_ciw_4spn,
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rv_codec_cj,
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rv_codec_cj_jal,
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rv_codec_cl_lw,
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rv_codec_cl_ld,
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rv_codec_cl_lq,
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rv_codec_cr,
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rv_codec_cr_mv,
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rv_codec_cr_jalr,
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rv_codec_cr_jr,
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rv_codec_cs,
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rv_codec_cs_sw,
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rv_codec_cs_sd,
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rv_codec_cs_sq,
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rv_codec_css_swsp,
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rv_codec_css_sdsp,
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rv_codec_css_sqsp,
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} rv_codec;
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typedef enum {
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rv_op_illegal,
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rv_op_lui,
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rv_op_auipc,
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rv_op_jal,
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rv_op_jalr,
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rv_op_beq,
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rv_op_bne,
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rv_op_blt,
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rv_op_bge,
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rv_op_bltu,
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rv_op_bgeu,
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rv_op_lb,
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rv_op_lh,
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rv_op_lw,
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rv_op_lbu,
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rv_op_lhu,
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rv_op_sb,
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rv_op_sh,
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rv_op_sw,
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rv_op_addi,
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rv_op_slti,
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rv_op_sltiu,
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rv_op_xori,
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rv_op_ori,
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rv_op_andi,
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rv_op_slli,
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rv_op_srli,
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rv_op_srai,
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rv_op_add,
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rv_op_sub,
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rv_op_sll,
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rv_op_slt,
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rv_op_sltu,
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rv_op_xor,
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rv_op_srl,
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rv_op_sra,
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rv_op_or,
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rv_op_and,
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rv_op_fence,
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rv_op_fence_i,
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rv_op_lwu,
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rv_op_ld,
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rv_op_sd,
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rv_op_addiw,
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rv_op_slliw,
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rv_op_srliw,
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rv_op_sraiw,
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rv_op_addw,
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rv_op_subw,
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rv_op_sllw,
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rv_op_srlw,
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rv_op_sraw,
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rv_op_ldu,
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rv_op_lq,
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rv_op_sq,
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rv_op_addid,
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rv_op_sllid,
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rv_op_srlid,
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rv_op_sraid,
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rv_op_addd,
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rv_op_subd,
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rv_op_slld,
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rv_op_srld,
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rv_op_srad,
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rv_op_mul,
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rv_op_mulh,
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rv_op_mulhsu,
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rv_op_mulhu,
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rv_op_div,
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rv_op_divu,
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rv_op_rem,
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rv_op_remu,
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rv_op_mulw,
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rv_op_divw,
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rv_op_divuw,
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rv_op_remw,
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rv_op_remuw,
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rv_op_muld,
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rv_op_divd,
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rv_op_divud,
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rv_op_remd,
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rv_op_remud,
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rv_op_lr_w,
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rv_op_sc_w,
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rv_op_amoswap_w,
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rv_op_amoadd_w,
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rv_op_amoxor_w,
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rv_op_amoor_w,
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rv_op_amoand_w,
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rv_op_amomin_w,
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rv_op_amomax_w,
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rv_op_amominu_w,
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rv_op_amomaxu_w,
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rv_op_lr_d,
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rv_op_sc_d,
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rv_op_amoswap_d,
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rv_op_amoadd_d,
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rv_op_amoxor_d,
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rv_op_amoor_d,
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rv_op_amoand_d,
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rv_op_amomin_d,
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rv_op_amomax_d,
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rv_op_amominu_d,
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rv_op_amomaxu_d,
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rv_op_lr_q,
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rv_op_sc_q,
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rv_op_amoswap_q,
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rv_op_amoadd_q,
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rv_op_amoxor_q,
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rv_op_amoor_q,
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rv_op_amoand_q,
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rv_op_amomin_q,
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rv_op_amomax_q,
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rv_op_amominu_q,
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rv_op_amomaxu_q,
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rv_op_ecall,
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rv_op_ebreak,
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rv_op_uret,
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rv_op_sret,
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rv_op_hret,
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rv_op_mret,
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rv_op_dret,
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rv_op_sfence_vm,
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rv_op_sfence_vma,
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rv_op_wfi,
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rv_op_csrrw,
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rv_op_csrrs,
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rv_op_csrrc,
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rv_op_csrrwi,
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rv_op_csrrsi,
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rv_op_csrrci,
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rv_op_flh,
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rv_op_fsh,
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rv_op_fmadd_h,
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rv_op_fmsub_h,
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rv_op_fnmsub_h,
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rv_op_fnmadd_h,
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rv_op_fadd_h,
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rv_op_fsub_h,
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rv_op_fmul_h,
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rv_op_fdiv_h,
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rv_op_fsgnj_h,
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rv_op_fsgnjn_h,
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rv_op_fsgnjx_h,
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rv_op_fmin_h,
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rv_op_fmax_h,
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rv_op_fsqrt_h,
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rv_op_fle_h,
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rv_op_flt_h,
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rv_op_feq_h,
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rv_op_fcvt_w_h,
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rv_op_fcvt_wu_h,
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rv_op_fcvt_h_w,
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rv_op_fcvt_h_wu,
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rv_op_fclass_h,
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rv_op_fcvt_l_h,
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rv_op_fcvt_lu_h,
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rv_op_fmv_x_h,
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rv_op_fcvt_h_l,
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rv_op_fcvt_h_lu,
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rv_op_fmv_h_x,
|
|
|
|
|
rv_op_fcvt_s_h,
|
|
|
|
|
rv_op_fcvt_h_s,
|
|
|
|
|
rv_op_fcvt_d_h,
|
|
|
|
|
rv_op_fcvt_h_d,
|
|
|
|
|
rv_op_fcvt_q_h,
|
|
|
|
|
rv_op_fcvt_h_q,
|
|
|
|
|
rv_op_fmv_h,
|
|
|
|
|
rv_op_fabs_h,
|
|
|
|
|
rv_op_fneg_h,
|
|
|
|
|
rv_op_flw,
|
|
|
|
|
rv_op_fsw,
|
|
|
|
|
rv_op_fmadd_s,
|
|
|
|
|
rv_op_fmsub_s,
|
|
|
|
|
rv_op_fnmsub_s,
|
|
|
|
|
rv_op_fnmadd_s,
|
|
|
|
|
rv_op_fadd_s,
|
|
|
|
|
rv_op_fsub_s,
|
|
|
|
|
rv_op_fmul_s,
|
|
|
|
|
rv_op_fdiv_s,
|
|
|
|
|
rv_op_fsgnj_s,
|
|
|
|
|
rv_op_fsgnjn_s,
|
|
|
|
|
rv_op_fsgnjx_s,
|
|
|
|
|
rv_op_fmin_s,
|
|
|
|
|
rv_op_fmax_s,
|
|
|
|
|
rv_op_fsqrt_s,
|
|
|
|
|
rv_op_fle_s,
|
|
|
|
|
rv_op_flt_s,
|
|
|
|
|
rv_op_feq_s,
|
|
|
|
|
rv_op_fcvt_w_s,
|
|
|
|
|
rv_op_fcvt_wu_s,
|
|
|
|
|
rv_op_fcvt_s_w,
|
|
|
|
|
rv_op_fcvt_s_wu,
|
|
|
|
|
rv_op_fmv_x_s,
|
|
|
|
|
rv_op_fclass_s,
|
|
|
|
|
rv_op_fmv_s_x,
|
|
|
|
|
rv_op_fcvt_l_s,
|
|
|
|
|
rv_op_fcvt_lu_s,
|
|
|
|
|
rv_op_fcvt_s_l,
|
|
|
|
|
rv_op_fcvt_s_lu,
|
|
|
|
|
rv_op_fld,
|
|
|
|
|
rv_op_fsd,
|
|
|
|
|
rv_op_fmadd_d,
|
|
|
|
|
rv_op_fmsub_d,
|
|
|
|
|
rv_op_fnmsub_d,
|
|
|
|
|
rv_op_fnmadd_d,
|
|
|
|
|
rv_op_fadd_d,
|
|
|
|
|
rv_op_fsub_d,
|
|
|
|
|
rv_op_fmul_d,
|
|
|
|
|
rv_op_fdiv_d,
|
|
|
|
|
rv_op_fsgnj_d,
|
|
|
|
|
rv_op_fsgnjn_d,
|
|
|
|
|
rv_op_fsgnjx_d,
|
|
|
|
|
rv_op_fmin_d,
|
|
|
|
|
rv_op_fmax_d,
|
|
|
|
|
rv_op_fcvt_s_d,
|
|
|
|
|
rv_op_fcvt_d_s,
|
|
|
|
|
rv_op_fsqrt_d,
|
|
|
|
|
rv_op_fle_d,
|
|
|
|
|
rv_op_flt_d,
|
|
|
|
|
rv_op_feq_d,
|
|
|
|
|
rv_op_fcvt_w_d,
|
|
|
|
|
rv_op_fcvt_wu_d,
|
|
|
|
|
rv_op_fcvt_d_w,
|
|
|
|
|
rv_op_fcvt_d_wu,
|
|
|
|
|
rv_op_fclass_d,
|
|
|
|
|
rv_op_fcvt_l_d,
|
|
|
|
|
rv_op_fcvt_lu_d,
|
|
|
|
|
rv_op_fmv_x_d,
|
|
|
|
|
rv_op_fcvt_d_l,
|
|
|
|
|
rv_op_fcvt_d_lu,
|
|
|
|
|
rv_op_fmv_d_x,
|
|
|
|
|
rv_op_flq,
|
|
|
|
|
rv_op_fsq,
|
|
|
|
|
rv_op_fmadd_q,
|
|
|
|
|
rv_op_fmsub_q,
|
|
|
|
|
rv_op_fnmsub_q,
|
|
|
|
|
rv_op_fnmadd_q,
|
|
|
|
|
rv_op_fadd_q,
|
|
|
|
|
rv_op_fsub_q,
|
|
|
|
|
rv_op_fmul_q,
|
|
|
|
|
rv_op_fdiv_q,
|
|
|
|
|
rv_op_fsgnj_q,
|
|
|
|
|
rv_op_fsgnjn_q,
|
|
|
|
|
rv_op_fsgnjx_q,
|
|
|
|
|
rv_op_fmin_q,
|
|
|
|
|
rv_op_fmax_q,
|
|
|
|
|
rv_op_fcvt_s_q,
|
|
|
|
|
rv_op_fcvt_q_s,
|
|
|
|
|
rv_op_fcvt_d_q,
|
|
|
|
|
rv_op_fcvt_q_d,
|
|
|
|
|
rv_op_fsqrt_q,
|
|
|
|
|
rv_op_fle_q,
|
|
|
|
|
rv_op_flt_q,
|
|
|
|
|
rv_op_feq_q,
|
|
|
|
|
rv_op_fcvt_w_q,
|
|
|
|
|
rv_op_fcvt_wu_q,
|
|
|
|
|
rv_op_fcvt_q_w,
|
|
|
|
|
rv_op_fcvt_q_wu,
|
|
|
|
|
rv_op_fclass_q,
|
|
|
|
|
rv_op_fcvt_l_q,
|
|
|
|
|
rv_op_fcvt_lu_q,
|
|
|
|
|
rv_op_fcvt_q_l,
|
|
|
|
|
rv_op_fcvt_q_lu,
|
|
|
|
|
rv_op_fmv_x_q,
|
|
|
|
|
rv_op_fmv_q_x,
|
|
|
|
|
rv_op_c_addi4spn,
|
|
|
|
|
rv_op_c_fld,
|
|
|
|
|
rv_op_c_lw,
|
|
|
|
|
rv_op_c_flw,
|
|
|
|
|
rv_op_c_fsd,
|
|
|
|
|
rv_op_c_sw,
|
|
|
|
|
rv_op_c_fsw,
|
|
|
|
|
rv_op_c_nop,
|
|
|
|
|
rv_op_c_addi,
|
|
|
|
|
rv_op_c_jal,
|
|
|
|
|
rv_op_c_li,
|
|
|
|
|
rv_op_c_addi16sp,
|
|
|
|
|
rv_op_c_lui,
|
|
|
|
|
rv_op_c_srli,
|
|
|
|
|
rv_op_c_srai,
|
|
|
|
|
rv_op_c_andi,
|
|
|
|
|
rv_op_c_sub,
|
|
|
|
|
rv_op_c_xor,
|
|
|
|
|
rv_op_c_or,
|
|
|
|
|
rv_op_c_and,
|
|
|
|
|
rv_op_c_subw,
|
|
|
|
|
rv_op_c_addw,
|
|
|
|
|
rv_op_c_j,
|
|
|
|
|
rv_op_c_beqz,
|
|
|
|
|
rv_op_c_bnez,
|
|
|
|
|
rv_op_c_slli,
|
|
|
|
|
rv_op_c_fldsp,
|
|
|
|
|
rv_op_c_lwsp,
|
|
|
|
|
rv_op_c_flwsp,
|
|
|
|
|
rv_op_c_jr,
|
|
|
|
|
rv_op_c_mv,
|
|
|
|
|
rv_op_c_ebreak,
|
|
|
|
|
rv_op_c_jalr,
|
|
|
|
|
rv_op_c_add,
|
|
|
|
|
rv_op_c_fsdsp,
|
|
|
|
|
rv_op_c_swsp,
|
|
|
|
|
rv_op_c_fswsp,
|
|
|
|
|
rv_op_c_ld,
|
|
|
|
|
rv_op_c_sd,
|
|
|
|
|
rv_op_c_addiw,
|
|
|
|
|
rv_op_c_ldsp,
|
|
|
|
|
rv_op_c_sdsp,
|
|
|
|
|
rv_op_c_lq,
|
|
|
|
|
rv_op_c_sq,
|
|
|
|
|
rv_op_c_lqsp,
|
|
|
|
|
rv_op_c_sqsp,
|
|
|
|
|
rv_op_nop,
|
|
|
|
|
rv_op_mv,
|
|
|
|
|
rv_op_not,
|
|
|
|
|
rv_op_neg,
|
|
|
|
|
rv_op_negw,
|
|
|
|
|
rv_op_sext_w,
|
|
|
|
|
rv_op_seqz,
|
|
|
|
|
rv_op_snez,
|
|
|
|
|
rv_op_sltz,
|
|
|
|
|
rv_op_sgtz,
|
|
|
|
|
rv_op_fmv_s,
|
|
|
|
|
rv_op_fabs_s,
|
|
|
|
|
rv_op_fneg_s,
|
|
|
|
|
rv_op_fmv_d,
|
|
|
|
|
rv_op_fabs_d,
|
|
|
|
|
rv_op_fneg_d,
|
|
|
|
|
rv_op_fmv_q,
|
|
|
|
|
rv_op_fabs_q,
|
|
|
|
|
rv_op_fneg_q,
|
|
|
|
|
rv_op_beqz,
|
|
|
|
|
rv_op_bnez,
|
|
|
|
|
rv_op_blez,
|
|
|
|
|
rv_op_bgez,
|
|
|
|
|
rv_op_bltz,
|
|
|
|
|
rv_op_bgtz,
|
|
|
|
|
rv_op_ble,
|
|
|
|
|
rv_op_bleu,
|
|
|
|
|
rv_op_bgt,
|
|
|
|
|
rv_op_bgtu,
|
|
|
|
|
rv_op_j,
|
|
|
|
|
rv_op_ret,
|
|
|
|
|
rv_op_jr,
|
|
|
|
|
rv_op_rdcycle,
|
|
|
|
|
rv_op_rdtime,
|
|
|
|
|
rv_op_rdinstret,
|
|
|
|
|
rv_op_rdcycleh,
|
|
|
|
|
rv_op_rdtimeh,
|
|
|
|
|
rv_op_rdinstreth,
|
|
|
|
|
rv_op_frcsr,
|
|
|
|
|
rv_op_frrm,
|
|
|
|
|
rv_op_frflags,
|
|
|
|
|
rv_op_fscsr,
|
|
|
|
|
rv_op_fsrm,
|
|
|
|
|
rv_op_fsflags,
|
|
|
|
|
rv_op_fsrmi,
|
|
|
|
|
rv_op_fsflagsi,
|
2023-07-31 00:45:36 +00:00
|
|
|
rv_op_add_uw,
|
|
|
|
|
rv_op_andn,
|
|
|
|
|
rv_op_bclr,
|
|
|
|
|
rv_op_bclri,
|
|
|
|
|
rv_op_bext,
|
|
|
|
|
rv_op_bexti,
|
|
|
|
|
rv_op_binv,
|
|
|
|
|
rv_op_binvi,
|
|
|
|
|
rv_op_bset,
|
|
|
|
|
rv_op_bseti,
|
|
|
|
|
rv_op_clmul,
|
|
|
|
|
rv_op_clmulh,
|
|
|
|
|
rv_op_clmulr,
|
|
|
|
|
rv_op_clz,
|
|
|
|
|
rv_op_clzw,
|
|
|
|
|
rv_op_cpop,
|
|
|
|
|
rv_op_cpopw,
|
|
|
|
|
rv_op_ctz,
|
|
|
|
|
rv_op_ctzw,
|
|
|
|
|
rv_op_max,
|
|
|
|
|
rv_op_maxu,
|
|
|
|
|
rv_op_min,
|
|
|
|
|
rv_op_minu,
|
|
|
|
|
rv_op_orc_b,
|
|
|
|
|
rv_op_orn,
|
|
|
|
|
rv_op_rev8,
|
|
|
|
|
rv_op_rol,
|
|
|
|
|
rv_op_rolw,
|
|
|
|
|
rv_op_ror,
|
|
|
|
|
rv_op_rori,
|
|
|
|
|
rv_op_roriw,
|
|
|
|
|
rv_op_rorw,
|
|
|
|
|
rv_op_sext_b,
|
|
|
|
|
rv_op_sext_h,
|
|
|
|
|
rv_op_sh1add,
|
|
|
|
|
rv_op_sh1add_uw,
|
|
|
|
|
rv_op_sh2add,
|
|
|
|
|
rv_op_sh2add_uw,
|
|
|
|
|
rv_op_sh3add,
|
|
|
|
|
rv_op_sh3add_uw,
|
|
|
|
|
rv_op_slli_uw,
|
|
|
|
|
rv_op_xnor,
|
|
|
|
|
rv_op_zext_h,
|
2022-12-30 19:36:32 +00:00
|
|
|
} rv_op;
|
|
|
|
|
|
|
|
|
|
/* structures */
|
|
|
|
|
|
|
|
|
|
typedef struct {
|
|
|
|
|
uint64_t pc;
|
|
|
|
|
uint64_t inst;
|
|
|
|
|
int32_t imm;
|
|
|
|
|
uint16_t op;
|
|
|
|
|
uint8_t codec;
|
|
|
|
|
uint8_t rd;
|
|
|
|
|
uint8_t rs1;
|
|
|
|
|
uint8_t rs2;
|
|
|
|
|
uint8_t rs3;
|
|
|
|
|
uint8_t rm;
|
|
|
|
|
uint8_t pred;
|
|
|
|
|
uint8_t succ;
|
|
|
|
|
uint8_t aq;
|
|
|
|
|
uint8_t rl;
|
|
|
|
|
} rv_decode;
|
|
|
|
|
|
|
|
|
|
/* functions */
|
|
|
|
|
|
|
|
|
|
size_t riscv_inst_length(rv_inst inst);
|
|
|
|
|
void riscv_inst_fetch(const uint8_t *data, rv_inst *instp, size_t *length);
|
|
|
|
|
void riscv_disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst);
|
|
|
|
|
|
|
|
|
|
#endif
|
