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x86jit: Add some notes for vector calls.

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Let's avoid the thunks to be more similar to other backends.
This commit is contained in:
Unknown W. Brackets 2023-08-23 08:20:22 -07:00
parent ef93b7547e
commit 00155790d6
2 changed files with 15 additions and 3 deletions
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13
Core/MIPS/x86/X64IRJit.h
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@ -29,6 +29,19 @@
#include "Core/MIPS/JitCommon/JitCommon.h"
#include "Core/MIPS/x86/X64IRRegCache.h"
#if PPSSPP_PLATFORM(WINDOWS) && (defined(_MSC_VER) || defined(__clang__) || defined(__INTEL_COMPILER))
#define X64JIT_XMM_CALL __vectorcall
#define X64JIT_USE_XMM_CALL 1
#elif PPSSPP_ARCH(AMD64) && !PPSSPP_PLATFORM(WINDOWS)
// SystemV ABI supports XMM registers.
#define X64JIT_XMM_CALL
#define X64JIT_USE_XMM_CALL 1
#else
// GCC on x86 doesn't support vectorcall.
#define X64JIT_XMM_CALL
#define X64JIT_USE_XMM_CALL 0
#endif
namespace MIPSComp {
class X64JitBackend : public Gen::XCodeBlock, public IRNativeBackend {

5
Core/MIPS/x86/X64IRRegCache.cpp
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@ -50,12 +50,11 @@ const int *X64IRRegCache::GetAllocationOrder(MIPSLoc type, MIPSMap flags, int &c
base = RAX;
static const int allocationOrder[] = {
// On x64, RCX and RDX are the first args. CallProtectedFunction() assumes they're not regcached.
#if PPSSPP_ARCH(AMD64)
#ifdef _WIN32
RSI, RDI, R8, R9, R10, R11, R12, R13,
RSI, RDI, R8, R9, R10, R11, R12, R13, RDX, RCX,
#else
RBP, R8, R9, R10, R11, R12, R13,
RBP, R8, R9, R10, R11, R12, R13, RDX, RCX,
#endif
// Intentionally last.
R15,