diff --git a/Core/MIPS/ARM/ArmRegCache.cpp b/Core/MIPS/ARM/ArmRegCache.cpp
index 773b2a56e3..3b720433e2 100644
--- a/Core/MIPS/ARM/ArmRegCache.cpp
+++ b/Core/MIPS/ARM/ArmRegCache.cpp
@@ -29,7 +29,7 @@ ArmRegCache::ArmRegCache(MIPSState *mips, MIPSComp::ArmJitOptions *options) : mi
 }
 
 void ArmRegCache::Init(ARMXEmitter *emitter) {
-	emit = emitter;
+	emit_ = emitter;
 }
 
 void ArmRegCache::Start(MIPSAnalyst::AnalysisResults &stats) {
@@ -98,14 +98,14 @@ allocate:
 			if (!(mapFlags & MAP_NOINIT)) {
 				if (mr[mipsReg].loc == ML_MEM) {
 					if (mipsReg != 0) {
-						emit->LDR((ARMReg)reg, CTXREG, GetMipsRegOffset(mipsReg));
+						emit_->LDR((ARMReg)reg, CTXREG, GetMipsRegOffset(mipsReg));
 					} else {
 						// If we get a request to load the zero register, at least we won't spend
 						// time on a memory access...
-						emit->MOV((ARMReg)reg, 0);
+						emit_->MOV((ARMReg)reg, 0);
 					}
 				} else if (mr[mipsReg].loc == ML_IMM) {
-					emit->MOVI2R((ARMReg)reg, mr[mipsReg].imm);
+					emit_->MOVI2R((ARMReg)reg, mr[mipsReg].imm);
 					ar[reg].isDirty = true;  // IMM is always dirty.
 				}
 			}
@@ -181,7 +181,7 @@ void ArmRegCache::FlushArmReg(ARMReg r) {
 	}
 	if (ar[r].mipsReg != -1) {
 		if (ar[r].isDirty && mr[ar[r].mipsReg].loc == ML_ARMREG)
-			emit->STR(r, CTXREG, GetMipsRegOffset(ar[r].mipsReg));
+			emit_->STR(r, CTXREG, GetMipsRegOffset(ar[r].mipsReg));
 		// IMMs won't be in an ARM reg.
 		mr[ar[r].mipsReg].loc = ML_MEM;
 		mr[ar[r].mipsReg].reg = INVALID_REG;
@@ -197,8 +197,8 @@ void ArmRegCache::FlushR(MIPSReg r) {
 	switch (mr[r].loc) {
 	case ML_IMM:
 		// IMM is always "dirty".
-		emit->MOVI2R(R0, mr[r].imm);
-		emit->STR(R0, CTXREG, GetMipsRegOffset(r));
+		emit_->MOVI2R(R0, mr[r].imm);
+		emit_->STR(R0, CTXREG, GetMipsRegOffset(r));
 		break;
 
 	case ML_ARMREG:
@@ -206,7 +206,7 @@ void ArmRegCache::FlushR(MIPSReg r) {
 			ERROR_LOG(HLE, "FlushMipsReg: MipsReg had bad ArmReg");
 		}
 		if (ar[mr[r].reg].isDirty) {
-			emit->STR((ARMReg)mr[r].reg, CTXREG, GetMipsRegOffset(r));
+			emit_->STR((ARMReg)mr[r].reg, CTXREG, GetMipsRegOffset(r));
 			ar[mr[r].reg].isDirty = false;
 		}
 		ar[mr[r].reg].mipsReg = -1;
diff --git a/Core/MIPS/ARM/ArmRegCache.h b/Core/MIPS/ARM/ArmRegCache.h
index d1cec8af3d..1408165205 100644
--- a/Core/MIPS/ARM/ArmRegCache.h
+++ b/Core/MIPS/ARM/ArmRegCache.h
@@ -104,7 +104,7 @@ public:
 
 	ARMReg R(int preg); // Returns a cached register
 
-	void SetEmitter(ARMXEmitter *emitter) { emit = emitter; }
+	void SetEmitter(ARMXEmitter *emitter) { emit_ = emitter; }
 
 	// For better log output only.
 	void SetCompilerPC(u32 compilerPC) { compilerPC_ = compilerPC; }
@@ -116,7 +116,7 @@ private:
 		
 	MIPSState *mips_;
 	MIPSComp::ArmJitOptions *options_;
-	ARMXEmitter *emit;
+	ARMXEmitter *emit_;
 	u32 compilerPC_;
 
 	enum {
diff --git a/Core/MIPS/ARM/ArmRegCacheFPU.cpp b/Core/MIPS/ARM/ArmRegCacheFPU.cpp
index 9576affedb..348813624a 100644
--- a/Core/MIPS/ARM/ArmRegCacheFPU.cpp
+++ b/Core/MIPS/ARM/ArmRegCacheFPU.cpp
@@ -28,7 +28,7 @@ ArmRegCacheFPU::ArmRegCacheFPU(MIPSState *mips) : mips_(mips), vr(mr + 32) {
 }
 
 void ArmRegCacheFPU::Init(ARMXEmitter *emitter) {
-	emit = emitter;
+	emit_ = emitter;
 }
 
 void ArmRegCacheFPU::Start(MIPSAnalyst::AnalysisResults &stats) {
@@ -93,7 +93,7 @@ allocate:
 			ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false;
 			if (!(mapFlags & MAP_NOINIT)) {
 				if (mr[mipsReg].loc == ML_MEM && mipsReg < TEMP0) {
-					emit->VLDR((ARMReg)(reg + S0), CTXREG, GetMipsRegOffset(mipsReg));
+					emit_->VLDR((ARMReg)(reg + S0), CTXREG, GetMipsRegOffset(mipsReg));
 				}
 			}
 			ar[reg].mipsReg = mipsReg;
@@ -221,7 +221,7 @@ void ArmRegCacheFPU::FlushArmReg(ARMReg r) {
 		if (ar[reg].isDirty && mr[ar[reg].mipsReg].loc == ML_ARMREG)
 		{
 			//INFO_LOG(HLE, "Flushing ARM reg %i", reg);
-			emit->VSTR(r, CTXREG, GetMipsRegOffset(ar[reg].mipsReg));
+			emit_->VSTR(r, CTXREG, GetMipsRegOffset(ar[reg].mipsReg));
 		}
 		// IMMs won't be in an ARM reg.
 		mr[ar[reg].mipsReg].loc = ML_MEM;
@@ -247,7 +247,7 @@ void ArmRegCacheFPU::FlushR(MIPSReg r) {
 		}
 		if (ar[mr[r].reg].isDirty) {
 			//INFO_LOG(HLE, "Flushing dirty reg %i", mr[r].reg);
-			emit->VSTR((ARMReg)(mr[r].reg + S0), CTXREG, GetMipsRegOffset(r));
+			emit_->VSTR((ARMReg)(mr[r].reg + S0), CTXREG, GetMipsRegOffset(r));
 			ar[mr[r].reg].isDirty = false;
 		}
 		ar[mr[r].reg].mipsReg = -1;
diff --git a/Core/MIPS/ARM/ArmRegCacheFPU.h b/Core/MIPS/ARM/ArmRegCacheFPU.h
index 80570bf7a0..d1415040a0 100644
--- a/Core/MIPS/ARM/ArmRegCacheFPU.h
+++ b/Core/MIPS/ARM/ArmRegCacheFPU.h
@@ -113,7 +113,7 @@ public:
 	void SpillLockV(const u8 *v, VectorSize vsz);
 	void SpillLockV(int vec, VectorSize vsz);
 
-	void SetEmitter(ARMXEmitter *emitter) { emit = emitter; }
+	void SetEmitter(ARMXEmitter *emitter) { emit_ = emitter; }
 
 	// For better log output only.
 	void SetCompilerPC(u32 compilerPC) { compilerPC_ = compilerPC; }
@@ -125,7 +125,7 @@ public:
 
 private:
 	MIPSState *mips_;
-	ARMXEmitter *emit;
+	ARMXEmitter *emit_;
 	u32 compilerPC_;
 
 	enum {
diff --git a/native b/native
index cdfa331775..d0442bc2a0 160000
--- a/native
+++ b/native
@@ -1 +1 @@
-Subproject commit cdfa331775a8edc170f89d3b4af5b0c51ed6195c
+Subproject commit d0442bc2a0eb53e5c7c9398a6e58f3df3e1f6de0