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riscv: Add bitmanip ops to disasm.
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parent
50ac61f362
commit
0d0029fc9d
@ -335,7 +335,7 @@ std::vector<std::string> DisassembleRV64(const u8 *data, int size) {
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// Force align in case we're somehow unaligned.
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len = 2 - ((uintptr_t)data & 1);
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invalid_count += (int)len;
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i +=(int) len;
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i += (int)len;
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continue;
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}
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@ -674,6 +674,49 @@ const rv_opcode_data opcode_data[] = {
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{ "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
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{ "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
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{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "clz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "clzw", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "cpop", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "cpopw", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "ctz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "ctzw", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "orc.b", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "rev8", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "roriw", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sext.b", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "sext.h", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "zext.h", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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};
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/* CSR names */
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@ -1091,6 +1134,18 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 1:
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switch (((inst >> 27) & 0b11111)) {
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case 0: op = rv_op_slli; break;
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case 5: op = rv_op_bseti; break;
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case 9: op = rv_op_bclri; break;
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case 12:
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switch (((inst >> 20) & 0b11111)) {
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case 0: op = rv_op_clz; break;
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case 1: op = rv_op_ctz; break;
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case 2: op = rv_op_cpop; break;
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case 4: op = rv_op_sext_b; break;
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case 5: op = rv_op_sext_h; break;
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}
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break;
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case 13: op = rv_op_binvi; break;
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}
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break;
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case 2: op = rv_op_slti; break;
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@ -1099,7 +1154,20 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 5:
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switch (((inst >> 27) & 0b11111)) {
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case 0: op = rv_op_srli; break;
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case 5:
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switch (((inst >> 20) & 0b1111111)) {
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case 7: op = rv_op_orc_b; break;
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}
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break;
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case 8: op = rv_op_srai; break;
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case 9: op = rv_op_bexti; break;
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case 12: op = rv_op_rori; break;
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case 13:
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switch (((inst >> 20) & 0b1111111)) {
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case 24: if (isa == rv32) op = rv_op_rev8; break;
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case 56: if (isa == rv64) op = rv_op_rev8; break;
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}
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break;
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}
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break;
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case 6: op = rv_op_ori; break;
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@ -1113,12 +1181,22 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 1:
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switch (((inst >> 25) & 0b1111111)) {
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case 0: op = rv_op_slliw; break;
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case 4: op = rv_op_slli_uw; break;
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case 5: op = rv_op_slli_uw; break;
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case 48:
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switch (((inst >> 20) & 0b11111)) {
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case 0: op = rv_op_clzw; break;
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case 1: op = rv_op_ctzw; break;
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case 2: op = rv_op_cpopw; break;
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}
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break;
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}
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break;
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case 5:
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switch (((inst >> 25) & 0b1111111)) {
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case 0: op = rv_op_srliw; break;
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case 32: op = rv_op_sraiw; break;
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case 48: op = rv_op_roriw; break;
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}
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break;
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}
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@ -1207,8 +1285,32 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 13: op = rv_op_divu; break;
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case 14: op = rv_op_rem; break;
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case 15: op = rv_op_remu; break;
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case 36:
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switch (((inst >> 20) & 0b11111)) {
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case 0: if (isa == rv32) op = rv_op_zext_h; break;
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}
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break;
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case 41: op = rv_op_clmul; break;
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case 42: op = rv_op_clmulr; break;
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case 43: op = rv_op_clmulh; break;
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case 44: op = rv_op_min; break;
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case 45: op = rv_op_minu; break;
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case 46: op = rv_op_max; break;
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case 47: op = rv_op_maxu; break;
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case 130: op = rv_op_sh1add; break;
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case 132: op = rv_op_sh2add; break;
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case 134: op = rv_op_sh3add; break;
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case 161: op = rv_op_bset; break;
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case 256: op = rv_op_sub; break;
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case 260: op = rv_op_xnor; break;
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case 261: op = rv_op_sra; break;
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case 262: op = rv_op_orn; break;
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case 263: op = rv_op_andn; break;
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case 289: op = rv_op_bclr; break;
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case 293: op = rv_op_bext; break;
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case 385: op = rv_op_rol; break;
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case 389: op = rv_op_ror; break;
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case 417: op = rv_op_binv; break;
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}
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break;
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case 13: op = rv_op_lui; break;
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@ -1222,8 +1324,19 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 13: op = rv_op_divuw; break;
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case 14: op = rv_op_remw; break;
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case 15: op = rv_op_remuw; break;
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case 32: op = rv_op_add_uw; break;
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case 36:
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switch (((inst >> 20) & 0b11111)) {
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case 0: if (isa == rv64) op = rv_op_zext_h; break;
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}
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break;
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case 130: op = rv_op_sh1add_uw; break;
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case 132: op = rv_op_sh2add_uw; break;
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case 134: op = rv_op_sh3add_uw; break;
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case 256: op = rv_op_subw; break;
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case 261: op = rv_op_sraw; break;
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case 385: op = rv_op_rolw; break;
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case 389: op = rv_op_rorw; break;
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}
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break;
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case 16:
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@ -524,6 +524,49 @@ typedef enum {
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rv_op_fsflags,
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rv_op_fsrmi,
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rv_op_fsflagsi,
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rv_op_add_uw,
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rv_op_andn,
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rv_op_bclr,
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rv_op_bclri,
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rv_op_bext,
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rv_op_bexti,
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rv_op_binv,
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rv_op_binvi,
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rv_op_bset,
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rv_op_bseti,
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rv_op_clmul,
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rv_op_clmulh,
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rv_op_clmulr,
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rv_op_clz,
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rv_op_clzw,
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rv_op_cpop,
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rv_op_cpopw,
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rv_op_ctz,
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rv_op_ctzw,
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rv_op_max,
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rv_op_maxu,
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rv_op_min,
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rv_op_minu,
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rv_op_orc_b,
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rv_op_orn,
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rv_op_rev8,
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rv_op_rol,
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rv_op_rolw,
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rv_op_ror,
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rv_op_rori,
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rv_op_roriw,
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rv_op_rorw,
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rv_op_sext_b,
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rv_op_sext_h,
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rv_op_sh1add,
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rv_op_sh1add_uw,
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rv_op_sh2add,
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rv_op_sh2add_uw,
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rv_op_sh3add,
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rv_op_sh3add_uw,
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rv_op_slli_uw,
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rv_op_xnor,
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rv_op_zext_h,
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} rv_op;
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/* structures */
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