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samplerjit: Use SSSE3/SSE4 in linear filtering.
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7aa9664d20
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1addf84e90
@ -1851,6 +1851,7 @@ void XEmitter::PINSRB(X64Reg dest, OpArg arg, u8 subreg) {WriteSSE41Op(0x66,
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void XEmitter::PINSRD(X64Reg dest, OpArg arg, u8 subreg) {WriteSSE41Op(0x66, 0x3A22, dest, arg, 1); Write8(subreg);}
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void XEmitter::PMADDWD(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xF5, dest, arg); }
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void XEmitter::PMADDUBSW(X64Reg dest, OpArg arg) {WriteSSSE3Op(0x66, 0x3804, dest, arg);}
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void XEmitter::PSADBW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xF6, dest, arg);}
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void XEmitter::PMAXSW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xEE, dest, arg); }
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@ -820,6 +820,7 @@ public:
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void PINSRD(X64Reg dest, OpArg arg, u8 subreg);
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void PMADDWD(X64Reg dest, OpArg arg);
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void PMADDUBSW(X64Reg dest, OpArg arg);
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void PSADBW(X64Reg dest, OpArg arg);
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void PMAXSW(X64Reg dest, OpArg arg);
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@ -113,8 +113,9 @@ private:
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const u8 *constVNext_ = nullptr;
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const u8 *constOnes32_ = nullptr;
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const u8 *constOnes16_ = nullptr;
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const u8 *const10All16_ = nullptr;
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const u8 *const10Low_ = nullptr;
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const u8 *const10All_ = nullptr;
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const u8 *const10All8_ = nullptr;
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std::unordered_map<SamplerID, NearestFunc> cache_;
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std::unordered_map<SamplerID, const u8 *> addresses_;
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@ -178,7 +178,7 @@ LinearFunc SamplerJitCache::CompileLinear(const SamplerID &id) {
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regCache_.Reset(true);
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// Let's drop some helpful constants here.
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const10All_ = AlignCode16();
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const10All16_ = AlignCode16();
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Write16(0x10); Write16(0x10); Write16(0x10); Write16(0x10);
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Write16(0x10); Write16(0x10); Write16(0x10); Write16(0x10);
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@ -186,6 +186,10 @@ LinearFunc SamplerJitCache::CompileLinear(const SamplerID &id) {
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Write16(0x10); Write16(0x10); Write16(0x10); Write16(0x10);
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Write16(0); Write16(0); Write16(0); Write16(0);
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const10All8_ = AlignCode16();
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for (int i = 0; i < 16; ++i)
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Write8(0x10);
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if (!id.hasAnyMips) {
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constWidth256f_ = AlignCode16();
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float w256f = (1 << id.width0Shift) * 256;
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@ -502,7 +506,7 @@ LinearFunc SamplerJitCache::CompileLinear(const SamplerID &id) {
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// Okay, next we need an inverse for color 0.
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X64Reg invFracReg = regCache_.Alloc(RegCache::VEC_TEMP1);
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MOVDQA(invFracReg, M(const10All_));
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MOVDQA(invFracReg, M(const10All16_));
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PSUBW(invFracReg, R(fracReg));
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// And multiply.
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@ -587,110 +591,189 @@ RegCache::Reg SamplerJitCache::GetGState() {
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bool SamplerJitCache::Jit_BlendQuad(const SamplerID &id, bool level1) {
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Describe(level1 ? "BlendQuadMips" : "BlendQuad");
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// First put the top RRRRRRRR LLLLLLLL into topReg, bottom into bottomReg.
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// Start with XXXX XXXX RRRR LLLL, and then expand 8 bits to 16 bits.
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// TODO: Maybe we can use PMADDUBSW?
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X64Reg topReg = regCache_.Alloc(RegCache::VEC_TEMP0);
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X64Reg bottomReg = regCache_.Alloc(RegCache::VEC_TEMP1);
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X64Reg quadReg = regCache_.Find(level1 ? RegCache::VEC_RESULT1 : RegCache::VEC_RESULT);
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if (!cpu_info.bSSE4_1) {
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if (cpu_info.bSSE4_1 && cpu_info.bSSSE3) {
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// Let's start by rearranging from TL TR BL BR like this:
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// ABCD EFGH IJKL MNOP -> AI BJ CK DL EM FN GO HP -> AIEM BJFN CKGO DLHP
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// This way, all the RGBAs are next to each other, and in order TL BL TR BR.
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X64Reg quadReg = regCache_.Find(level1 ? RegCache::VEC_RESULT1 : RegCache::VEC_RESULT);
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X64Reg tempArrangeReg = regCache_.Alloc(RegCache::VEC_TEMP0);
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PSHUFD(tempArrangeReg, R(quadReg), _MM_SHUFFLE(3, 2, 3, 2));
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PUNPCKLBW(quadReg, R(tempArrangeReg));
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// Okay, that's top and bottom interleaved, now for left and right.
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PSHUFD(tempArrangeReg, R(quadReg), _MM_SHUFFLE(3, 2, 3, 2));
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PUNPCKLWD(quadReg, R(tempArrangeReg));
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regCache_.Release(tempArrangeReg, RegCache::VEC_TEMP0);
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// Next up, we want to multiply and add using a repeated TB frac pair.
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// That's (0x10 - frac_v) in byte 1, frac_v in byte 2, repeating.
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X64Reg fracReg = regCache_.Alloc(RegCache::VEC_TEMP0);
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X64Reg zeroReg = GetZeroVec();
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PSHUFD(topReg, R(quadReg), _MM_SHUFFLE(0, 0, 1, 0));
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PSHUFD(bottomReg, R(quadReg), _MM_SHUFFLE(0, 0, 3, 2));
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PUNPCKLBW(topReg, R(zeroReg));
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PUNPCKLBW(bottomReg, R(zeroReg));
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regCache_.Unlock(zeroReg, RegCache::VEC_ZERO);
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} else {
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PSHUFD(bottomReg, R(quadReg), _MM_SHUFFLE(0, 0, 3, 2));
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PMOVZXBW(topReg, R(quadReg));
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PMOVZXBW(bottomReg, R(bottomReg));
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}
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if (!level1) {
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regCache_.Unlock(quadReg, RegCache::VEC_RESULT);
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regCache_.ForceRelease(RegCache::VEC_RESULT);
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}
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// Grab frac_u and spread to lower (L) lanes.
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X64Reg fracReg = regCache_.Alloc(RegCache::VEC_TEMP2);
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X64Reg fracMulReg = regCache_.Alloc(RegCache::VEC_TEMP3);
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if (level1) {
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MOVD_xmm(fracReg, MDisp(RSP, stackArgPos_ + stackFracUV1Offset_));
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} else {
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X64Reg fracUReg = regCache_.Find(RegCache::GEN_ARG_FRAC_U);
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MOVD_xmm(fracReg, R(fracUReg));
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regCache_.Unlock(fracUReg, RegCache::GEN_ARG_FRAC_U);
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regCache_.ForceRelease(RegCache::GEN_ARG_FRAC_U);
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}
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PSHUFLW(fracReg, R(fracReg), _MM_SHUFFLE(0, 0, 0, 0));
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// Now subtract 0x10 - frac_u in the L lanes only: 00000000 LLLLLLLL.
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MOVDQA(fracMulReg, M(const10Low_));
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PSUBW(fracMulReg, R(fracReg));
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// Then we just shift and OR in the original frac_u.
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PSLLDQ(fracReg, 8);
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POR(fracMulReg, R(fracReg));
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regCache_.Release(fracReg, RegCache::VEC_TEMP2);
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// Okay, we have 8-bits in the top and bottom rows for the color.
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// Multiply by frac to get 12, which we keep for the next stage.
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PMULLW(topReg, R(fracMulReg));
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PMULLW(bottomReg, R(fracMulReg));
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regCache_.Release(fracMulReg, RegCache::VEC_TEMP3);
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// Time for frac_v. This time, we want it in all 8 lanes.
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fracReg = regCache_.Alloc(RegCache::VEC_TEMP2);
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X64Reg fracTopReg = regCache_.Alloc(RegCache::VEC_TEMP3);
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if (level1) {
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MOVD_xmm(fracReg, MDisp(RSP, stackArgPos_ + stackFracUV1Offset_ + 4));
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} else {
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X64Reg fracVReg = regCache_.Find(RegCache::GEN_ARG_FRAC_V);
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MOVD_xmm(fracReg, R(fracVReg));
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regCache_.Unlock(fracVReg, RegCache::GEN_ARG_FRAC_V);
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regCache_.ForceRelease(RegCache::GEN_ARG_FRAC_V);
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}
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PSHUFLW(fracReg, R(fracReg), _MM_SHUFFLE(0, 0, 0, 0));
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PSHUFD(fracReg, R(fracReg), _MM_SHUFFLE(0, 0, 0, 0));
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// Now, inverse fracReg into fracTopReg for the top row.
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MOVDQA(fracTopReg, M(const10All_));
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PSUBW(fracTopReg, R(fracReg));
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// We had 12, plus 4 frac, that gives us 16.
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PMULLW(bottomReg, R(fracReg));
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PMULLW(topReg, R(fracTopReg));
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regCache_.Release(fracReg, RegCache::VEC_TEMP2);
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regCache_.Release(fracTopReg, RegCache::VEC_TEMP3);
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// Finally, time to sum them all up and divide by 256 to get back to 8 bits.
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PADDUSW(bottomReg, R(topReg));
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regCache_.Release(topReg, RegCache::VEC_TEMP0);
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bool changeSuccess = true;
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if (level1) {
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PSHUFD(quadReg, R(bottomReg), _MM_SHUFFLE(3, 2, 3, 2));
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PADDUSW(quadReg, R(bottomReg));
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PSRLW(quadReg, 8);
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regCache_.Release(bottomReg, RegCache::VEC_TEMP1);
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regCache_.Unlock(quadReg, RegCache::VEC_RESULT1);
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} else {
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changeSuccess = regCache_.ChangeReg(XMM0, RegCache::VEC_RESULT);
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if (!changeSuccess) {
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_assert_msg_(XMM0 == bottomReg, "Unexpected other reg locked as destReg");
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X64Reg otherReg = regCache_.Alloc(RegCache::VEC_TEMP0);
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PSHUFD(otherReg, R(bottomReg), _MM_SHUFFLE(3, 2, 3, 2));
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PADDUSW(bottomReg, R(otherReg));
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regCache_.Release(otherReg, RegCache::VEC_TEMP0);
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regCache_.Release(bottomReg, RegCache::VEC_TEMP1);
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// Okay, now it can be changed.
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regCache_.ChangeReg(XMM0, RegCache::VEC_RESULT);
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if (level1) {
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MOVD_xmm(fracReg, MDisp(RSP, stackArgPos_ + stackFracUV1Offset_ + 4));
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} else {
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PSHUFD(XMM0, R(bottomReg), _MM_SHUFFLE(3, 2, 3, 2));
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PADDUSW(XMM0, R(bottomReg));
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regCache_.Release(bottomReg, RegCache::VEC_TEMP1);
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X64Reg fracVReg = regCache_.Find(RegCache::GEN_ARG_FRAC_V);
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MOVD_xmm(fracReg, R(fracVReg));
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regCache_.Unlock(fracVReg, RegCache::GEN_ARG_FRAC_V);
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regCache_.ForceRelease(RegCache::GEN_ARG_FRAC_V);
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}
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PSHUFB(fracReg, R(zeroReg));
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regCache_.Unlock(zeroReg, RegCache::VEC_ZERO);
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// Now, inverse fracReg, then interleave into the actual multiplier.
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// This gives us the repeated TB pairs we wanted.
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X64Reg multTBReg = regCache_.Alloc(RegCache::VEC_TEMP1);
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MOVDQA(multTBReg, M(const10All8_));
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PSUBB(multTBReg, R(fracReg));
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PUNPCKLBW(multTBReg, R(fracReg));
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regCache_.Release(fracReg, RegCache::VEC_TEMP0);
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// Now we can multiply and add paired lanes in one go.
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// Note that since T+B=0x10, this gives us exactly 12 bits.
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PMADDUBSW(quadReg, R(multTBReg));
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regCache_.Release(multTBReg, RegCache::VEC_TEMP1);
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// With that done, we need to multiply by LR, or rather 0L0R, and sum again.
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// Since RRRR was all next to each other, this gives us a clean total R.
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fracReg = regCache_.Alloc(RegCache::VEC_TEMP0);
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if (level1) {
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MOVD_xmm(fracReg, MDisp(RSP, stackArgPos_ + stackFracUV1Offset_));
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} else {
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X64Reg fracUReg = regCache_.Find(RegCache::GEN_ARG_FRAC_U);
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MOVD_xmm(fracReg, R(fracUReg));
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regCache_.Unlock(fracUReg, RegCache::GEN_ARG_FRAC_U);
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regCache_.ForceRelease(RegCache::GEN_ARG_FRAC_U);
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}
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// We can ignore the high bits, since we'll interleave those away anyway.
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PSHUFLW(fracReg, R(fracReg), _MM_SHUFFLE(0, 0, 0, 0));
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// Again, we're inversing into an interleaved multiplier. L is the inversed one.
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// 0L0R is (0x10 - frac_u), frac_u - 2x16 repeated four times.
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X64Reg multLRReg = regCache_.Alloc(RegCache::VEC_TEMP1);
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MOVDQA(multLRReg, M(const10All16_));
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PSUBW(multLRReg, R(fracReg));
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PUNPCKLWD(multLRReg, R(fracReg));
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regCache_.Release(fracReg, RegCache::VEC_TEMP0);
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// This gives us RGBA as dwords, but they're all shifted left by 8 from the multiplies.
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PMADDWD(quadReg, R(multLRReg));
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PSRLD(quadReg, 8);
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regCache_.Release(multLRReg, RegCache::VEC_TEMP1);
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// Shrink to 16-bit, it's more convenient for later.
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PACKSSDW(quadReg, R(quadReg));
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if (level1) {
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regCache_.Unlock(quadReg, RegCache::VEC_RESULT1);
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} else {
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MOVDQA(XMM0, R(quadReg));
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regCache_.Unlock(quadReg, RegCache::VEC_RESULT);
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regCache_.ForceRelease(RegCache::VEC_RESULT);
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bool changeSuccess = regCache_.ChangeReg(XMM0, RegCache::VEC_RESULT);
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_assert_msg_(changeSuccess, "Unexpected reg locked as destReg");
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}
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} else {
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X64Reg topReg = regCache_.Alloc(RegCache::VEC_TEMP0);
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X64Reg bottomReg = regCache_.Alloc(RegCache::VEC_TEMP1);
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X64Reg quadReg = regCache_.Find(level1 ? RegCache::VEC_RESULT1 : RegCache::VEC_RESULT);
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if (!cpu_info.bSSE4_1) {
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X64Reg zeroReg = GetZeroVec();
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PSHUFD(topReg, R(quadReg), _MM_SHUFFLE(0, 0, 1, 0));
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PSHUFD(bottomReg, R(quadReg), _MM_SHUFFLE(0, 0, 3, 2));
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PUNPCKLBW(topReg, R(zeroReg));
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PUNPCKLBW(bottomReg, R(zeroReg));
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regCache_.Unlock(zeroReg, RegCache::VEC_ZERO);
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} else {
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PSHUFD(bottomReg, R(quadReg), _MM_SHUFFLE(0, 0, 3, 2));
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PMOVZXBW(topReg, R(quadReg));
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PMOVZXBW(bottomReg, R(bottomReg));
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}
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if (!level1) {
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regCache_.Unlock(quadReg, RegCache::VEC_RESULT);
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regCache_.ForceRelease(RegCache::VEC_RESULT);
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}
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PSRLW(XMM0, 8);
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// Grab frac_u and spread to lower (L) lanes.
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X64Reg fracReg = regCache_.Alloc(RegCache::VEC_TEMP2);
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X64Reg fracMulReg = regCache_.Alloc(RegCache::VEC_TEMP3);
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if (level1) {
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MOVD_xmm(fracReg, MDisp(RSP, stackArgPos_ + stackFracUV1Offset_));
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} else {
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X64Reg fracUReg = regCache_.Find(RegCache::GEN_ARG_FRAC_U);
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MOVD_xmm(fracReg, R(fracUReg));
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regCache_.Unlock(fracUReg, RegCache::GEN_ARG_FRAC_U);
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regCache_.ForceRelease(RegCache::GEN_ARG_FRAC_U);
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}
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PSHUFLW(fracReg, R(fracReg), _MM_SHUFFLE(0, 0, 0, 0));
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// Now subtract 0x10 - frac_u in the L lanes only: 00000000 LLLLLLLL.
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MOVDQA(fracMulReg, M(const10Low_));
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PSUBW(fracMulReg, R(fracReg));
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// Then we just shift and OR in the original frac_u.
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PSLLDQ(fracReg, 8);
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POR(fracMulReg, R(fracReg));
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regCache_.Release(fracReg, RegCache::VEC_TEMP2);
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// Okay, we have 8-bits in the top and bottom rows for the color.
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// Multiply by frac to get 12, which we keep for the next stage.
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PMULLW(topReg, R(fracMulReg));
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PMULLW(bottomReg, R(fracMulReg));
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regCache_.Release(fracMulReg, RegCache::VEC_TEMP3);
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// Time for frac_v. This time, we want it in all 8 lanes.
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fracReg = regCache_.Alloc(RegCache::VEC_TEMP2);
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X64Reg fracTopReg = regCache_.Alloc(RegCache::VEC_TEMP3);
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if (level1) {
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MOVD_xmm(fracReg, MDisp(RSP, stackArgPos_ + stackFracUV1Offset_ + 4));
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} else {
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X64Reg fracVReg = regCache_.Find(RegCache::GEN_ARG_FRAC_V);
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MOVD_xmm(fracReg, R(fracVReg));
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regCache_.Unlock(fracVReg, RegCache::GEN_ARG_FRAC_V);
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regCache_.ForceRelease(RegCache::GEN_ARG_FRAC_V);
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}
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PSHUFLW(fracReg, R(fracReg), _MM_SHUFFLE(0, 0, 0, 0));
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PSHUFD(fracReg, R(fracReg), _MM_SHUFFLE(0, 0, 0, 0));
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// Now, inverse fracReg into fracTopReg for the top row.
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MOVDQA(fracTopReg, M(const10All16_));
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PSUBW(fracTopReg, R(fracReg));
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// We had 12, plus 4 frac, that gives us 16.
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PMULLW(bottomReg, R(fracReg));
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PMULLW(topReg, R(fracTopReg));
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regCache_.Release(fracReg, RegCache::VEC_TEMP2);
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regCache_.Release(fracTopReg, RegCache::VEC_TEMP3);
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// Finally, time to sum them all up and divide by 256 to get back to 8 bits.
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PADDUSW(bottomReg, R(topReg));
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regCache_.Release(topReg, RegCache::VEC_TEMP0);
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if (level1) {
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PSHUFD(quadReg, R(bottomReg), _MM_SHUFFLE(3, 2, 3, 2));
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PADDUSW(quadReg, R(bottomReg));
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PSRLW(quadReg, 8);
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regCache_.Release(bottomReg, RegCache::VEC_TEMP1);
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regCache_.Unlock(quadReg, RegCache::VEC_RESULT1);
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} else {
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bool changeSuccess = regCache_.ChangeReg(XMM0, RegCache::VEC_RESULT);
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if (!changeSuccess) {
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_assert_msg_(XMM0 == bottomReg, "Unexpected other reg locked as destReg");
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X64Reg otherReg = regCache_.Alloc(RegCache::VEC_TEMP0);
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PSHUFD(otherReg, R(bottomReg), _MM_SHUFFLE(3, 2, 3, 2));
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PADDUSW(bottomReg, R(otherReg));
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regCache_.Release(otherReg, RegCache::VEC_TEMP0);
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regCache_.Release(bottomReg, RegCache::VEC_TEMP1);
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// Okay, now it can be changed.
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regCache_.ChangeReg(XMM0, RegCache::VEC_RESULT);
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} else {
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PSHUFD(XMM0, R(bottomReg), _MM_SHUFFLE(3, 2, 3, 2));
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PADDUSW(XMM0, R(bottomReg));
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regCache_.Release(bottomReg, RegCache::VEC_TEMP1);
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}
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PSRLW(XMM0, 8);
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user