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Delete the lookup table version of vh2f

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This commit is contained in:
Henrik Rydgard 2013-09-28 22:11:24 +02:00
parent 7ca6d73857
commit 20174d9410
3 changed files with 2 additions and 95 deletions
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90
Core/MIPS/x86/CompVFPU.cpp
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@ -17,6 +17,7 @@
#include <cmath>
#include <limits>
#include <xmmintrin.h>
#include "base/logging.h"
#include "math/math_util.h"
@ -1083,90 +1084,6 @@ void Jit::Comp_Vi2f(MIPSOpcode op) {
fpr.ReleaseSpillLocks();
}
#if 0
// One possible approach
// Uses lookup tables to decode half floats. Not really sure how bad the CPU cache impact will be...
void Jit::Comp_Vh2f(MIPSOpcode op) {
CONDITIONAL_DISABLE;
if (js.HasUnknownPrefix())
DISABLE;
VectorSize sz = GetVecSize(op);
VectorSize outsize;
switch (sz) {
case V_Single:
outsize = V_Pair;
break;
case V_Pair:
outsize = V_Quad;
break;
}
u8 sregs[4], dregs[4];
GetVectorRegsPrefixS(sregs, sz, _VS);
GetVectorRegsPrefixD(dregs, outsize, _VD);
switch (sz) {
case V_Single:
// Flush so we can access it with integer instructions
// Grab ECX as a secondary working register
gpr.FlushLockX(ECX);
fpr.StoreFromRegisterV(sregs[0]);
MOV(32, R(EAX), fpr.V(sregs[0]));
fpr.MapRegsV(dregs, outsize, MAP_NOINIT | MAP_DIRTY);
//XOR(32, R(EAX), R(EAX));
MOV(32, R(ECX), R(EAX));
AND(32, R(EAX), Imm32(0xFFFF));
SHR(32, R(ECX), Imm8(16));
#ifdef _M_IX86
MOVSS(fpr.VX(dregs[0]), MScaled(EAX, 4, (u32)halfToFloat_));
MOVSS(fpr.VX(dregs[1]), MScaled(ECX, 4, (u32)halfToFloat_));
#endif
break;
case V_Pair:
// Flush so we can access it with integer instructions
// Grab ECX and EDX as a secondary/third working register
gpr.FlushLockX(ECX, EDX);
fpr.StoreFromRegisterV(sregs[0]);
fpr.StoreFromRegisterV(sregs[1]);
MOV(32, R(EAX), fpr.V(sregs[0]));
MOV(32, R(EDX), fpr.V(sregs[1]));
fpr.MapRegsV(dregs, outsize, MAP_NOINIT | MAP_DIRTY);
//XOR(32, R(EAX), R(EAX));
MOV(32, R(ECX), R(EAX));
AND(32, R(EAX), Imm32(0xFFFF));
SHR(32, R(ECX), Imm8(16));
#ifdef _M_IX86
MOVSS(fpr.VX(dregs[0]), MScaled(EAX, 4, (u32)halfToFloat_));
MOVSS(fpr.VX(dregs[1]), MScaled(ECX, 4, (u32)halfToFloat_));
#endif
//XOR(32, R(EAX), R(EAX));
MOV(32, R(ECX), R(EDX));
AND(32, R(EDX), Imm32(0xFFFF));
SHR(32, R(ECX), Imm8(16));
#ifdef _M_IX86
MOVSS(fpr.VX(dregs[2]), MScaled(EDX, 4, (u32)halfToFloat_));
MOVSS(fpr.VX(dregs[3]), MScaled(ECX, 4, (u32)halfToFloat_));
#endif
break;
case V_Triple:
case V_Quad:
_dbg_assert_msg_(CPU, 0, "Trying to interpret Int_Vh2f instruction that can't be interpreted");
break;
}
ApplyPrefixD(dregs, outsize);
gpr.UnlockAllX();
fpr.ReleaseSpillLocks();
}
#else
#undef CONST
// Planning for true SIMD
// Sequence for gathering sparse registers into one SIMD:
@ -1192,7 +1109,7 @@ void Jit::Comp_Vh2f(MIPSOpcode op) {
// Translation of ryg's half_to_float5_SSE2
void Jit::Comp_Vh2f(MIPSOpcode op) {
#define SSE_CONST4(name, val) static const __declspec(align(16)) u32 name[4] = { (val), (val), (val), (val) }
#define SSE_CONST4(name, val) static const u32 MEMORY_ALIGNED16(name[4]) = { (val), (val), (val), (val) }
SSE_CONST4(mask_nosign, 0x7fff);
SSE_CONST4(magic, (254 - 15) << 23);
@ -1267,9 +1184,6 @@ void Jit::Comp_Vh2f(MIPSOpcode op) {
fpr.ReleaseSpillLocks();
}
#endif
extern const double mulTableVf2i[32] = {
(1ULL<<0),(1ULL<<1),(1ULL<<2),(1ULL<<3),
(1ULL<<4),(1ULL<<5),(1ULL<<6),(1ULL<<7),

5
Core/MIPS/x86/Jit.cpp
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@ -118,16 +118,11 @@ Jit::Jit(MIPSState *mips) : blocks(mips, this), mips_(mips)
fpr.SetEmitter(this);
AllocCodeSpace(1024 * 1024 * 16);
asm_.Init(mips, this);
halfToFloat_ = new float[65536];
for (int i = 0; i < 65536; i++) {
halfToFloat_[i] = ExpandHalf((u16)i);
}
// TODO: If it becomes possible to switch from the interpreter, this should be set right.
js.startDefaultPrefix = true;
}
Jit::~Jit() {
delete [] halfToFloat_;
}
void Jit::DoState(PointerWrap &p)

2
Core/MIPS/x86/Jit.h
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@ -340,8 +340,6 @@ private:
MIPSState *mips_;
float *halfToFloat_; // lookup table.
class JitSafeMem {
public:
JitSafeMem(Jit *jit, MIPSGPReg raddr, s32 offset, u32 alignMask = 0xFFFFFFFF);