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Return the correct value for fcr0/fir.

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This is what the PSP actually returns, it's read only.
This commit is contained in:
Unknown W. Brackets 2013-11-13 22:41:25 -08:00
parent 98fb2e0402
commit 26f5922174
5 changed files with 17 additions and 15 deletions
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8
Core/HLE/sceKernelThread.cpp
View File

@ -520,7 +520,7 @@ public:
virtual void DoState(PointerWrap &p)
{
auto s = p.Section("Thread", 1, 2);
auto s = p.Section("Thread", 1, 3);
if (!s)
return;
@ -531,6 +531,11 @@ public:
p.Do(currentMipscallId);
p.Do(currentCallbackId);
p.Do(context);
if (s <= 2)
{
context.other[4] = context.other[5];
context.other[3] = context.other[4];
}
p.Do(callbacks);
@ -1928,7 +1933,6 @@ void ThreadContext::reset()
vfpuCtrl[VFPU_CTRL_RCX6] = 0x3f800000;
vfpuCtrl[VFPU_CTRL_RCX7] = 0x3f800000;
fpcond = 0;
fcr0 = 0;
fcr31 = 0;
hi = 0xDEADBEEF;
lo = 0xDEADBEEF;

1
Core/HLE/sceKernelThread.h
View File

@ -132,7 +132,6 @@ struct ThreadContext
u32 hi;
u32 lo;
u32 fcr0;
u32 fcr31;
u32 fpcond;
};

10
Core/MIPS/ARM/ArmCompFPU.cpp
View File

@ -339,8 +339,7 @@ void Jit::Comp_mxc1(MIPSOpcode op)
return;
case 2: //cfc1
if (fs == 31)
{
if (fs == 31) {
gpr.MapDirtyIn(rt, MIPS_REG_FPCOND);
LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
#ifdef HAVE_ARMV7
@ -350,11 +349,8 @@ void Jit::Comp_mxc1(MIPSOpcode op)
ANDI2R(gpr.R(rt), gpr.R(rt), ~(0x1 << 23), R1); // R1 won't be used, this turns into a simple BIC.
ORR(gpr.R(rt), gpr.R(rt), Operand2(R0, ST_LSL, 23));
#endif
}
else if (fs == 0)
{
gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr0));
} else if (fs == 0) {
gpr.SetImm(rt, MIPSState::FCR0_VALUE);
}
return;

10
Core/MIPS/MIPS.cpp
View File

@ -134,7 +134,6 @@ void MIPSState::Reset()
hi = 0;
lo = 0;
fpcond = 0;
fcr0 = 0;
fcr31 = 0;
debugCount = 0;
currentMIPS = this;
@ -147,7 +146,7 @@ void MIPSState::Reset()
}
void MIPSState::DoState(PointerWrap &p) {
auto s = p.Section("MIPSState", 1);
auto s = p.Section("MIPSState", 1, 2);
if (!s)
return;
@ -169,7 +168,10 @@ void MIPSState::DoState(PointerWrap &p) {
p.Do(hi);
p.Do(lo);
p.Do(fpcond);
p.Do(fcr0);
if (s <= 1) {
u32 fcr0_unusued = 0;
p.Do(fcr0_unusued);
}
p.Do(fcr31);
p.Do(rng.m_w);
p.Do(rng.m_z);
@ -225,7 +227,7 @@ u32 MIPSState::ReadFCR(int reg)
}
else if (reg == 0)
{
return fcr0;
return FCR0_VALUE;
}
else
{

3
Core/MIPS/MIPS.h
View File

@ -146,7 +146,6 @@ public:
u32 hi;
u32 lo;
u32 fcr0;
u32 fcr31; //fpu control register
u32 fpcond; // cache the cond flag of fcr31 (& 1 << 23)
};
@ -165,6 +164,8 @@ public:
// Debug stuff
u32 debugCount; // can be used to count basic blocks before crashes, etc.
static const u32 FCR0_VALUE = 0x00003351;
void WriteFCR(int reg, int value);
u32 ReadFCR(int reg);