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mips: Clean up MIPSXEmitter a bit.

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Don't even want dangerous funcs like SUB().

Keeping things in opcode order at least locally so it doesn't get
confusing to maintain.  Also fixed a bunch of missing asserts.
This commit is contained in:
Unknown W. Brackets 2014-11-18 07:47:06 -08:00
parent 4167b66808
commit 29365e6775
2 changed files with 71 additions and 49 deletions
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94
Common/MipsEmitter.cpp
View File

@ -113,7 +113,7 @@ void MIPSXEmitter::JAL(const void *func) {
FixupBranch MIPSXEmitter::BEQ(MIPSReg rs, MIPSReg rt) { FixupBranch MIPSXEmitter::BEQ(MIPSReg rs, MIPSReg rt) {
// 000100 sssss ttttt iiiiiiiiiiiiiii (fix up) // 000100 sssss ttttt iiiiiiiiiiiiiii (fix up)
_dbg_assert_msg_(JIT, rs < F_BASE, "Bad emitter arguments"); _dbg_assert_msg_(JIT, rs < F_BASE && rt < F_BASE, "Bad emitter arguments");
FixupBranch b = MakeFixupBranch(BRANCH_16); FixupBranch b = MakeFixupBranch(BRANCH_16);
Write32Fields(26, 0x04, 21, rs, 16, rt); Write32Fields(26, 0x04, 21, rs, 16, rt);
return b; return b;
@ -125,7 +125,7 @@ void MIPSXEmitter::BEQ(MIPSReg rs, MIPSReg rt, const void *func) {
FixupBranch MIPSXEmitter::BNE(MIPSReg rs, MIPSReg rt) { FixupBranch MIPSXEmitter::BNE(MIPSReg rs, MIPSReg rt) {
// 000101 sssss ttttt iiiiiiiiiiiiiii (fix up) // 000101 sssss ttttt iiiiiiiiiiiiiii (fix up)
_dbg_assert_msg_(JIT, rs < F_BASE, "Bad emitter arguments"); _dbg_assert_msg_(JIT, rs < F_BASE && rt < F_BASE, "Bad emitter arguments");
FixupBranch b = MakeFixupBranch(BRANCH_16); FixupBranch b = MakeFixupBranch(BRANCH_16);
Write32Fields(26, 0x05, 21, rs, 16, rt); Write32Fields(26, 0x05, 21, rs, 16, rt);
return b; return b;
@ -219,16 +219,48 @@ void MIPSXEmitter::SLL(MIPSReg rd, MIPSReg rt, u8 sa) {
Write32Fields(26, 0x00, 16, rt, 11, rd, 6, sa & 0x1f, 0, 0x00); Write32Fields(26, 0x00, 16, rt, 11, rd, 6, sa & 0x1f, 0, 0x00);
} }
void MIPSXEmitter::SRL(MIPSReg rd, MIPSReg rt, u8 sa) {
// 000000 xxxxx ttttt ddddd aaaaa 000010
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && sa <= 0x1f, "Bad emitter arguments");
Write32Fields(26, 0x00, 16, rt, 11, rd, 6, sa & 0x1f, 0, 0x02);
}
void MIPSXEmitter::SRA(MIPSReg rd, MIPSReg rt, u8 sa) {
// 000000 xxxxx ttttt ddddd aaaaa 000011
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && sa <= 0x1f, "Bad emitter arguments");
Write32Fields(26, 0x00, 16, rt, 11, rd, 6, sa & 0x1f, 0, 0x03);
}
void MIPSXEmitter::SLLV(MIPSReg rd, MIPSReg rt, MIPSReg rs) { void MIPSXEmitter::SLLV(MIPSReg rd, MIPSReg rt, MIPSReg rs) {
// 000000 sssss ttttt ddddd 00000000100 // 000000 sssss ttttt ddddd xxxxx 000100
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && rs < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x04); Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x04);
} }
void MIPSXEmitter::SRLV(MIPSReg rd, MIPSReg rt, MIPSReg rs) {
// 000000 sssss ttttt ddddd xxxxx 000110
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && rs < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x06);
}
void MIPSXEmitter::SRAV(MIPSReg rd, MIPSReg rt, MIPSReg rs) {
// 000000 sssss ttttt ddddd xxxxx 000111
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && rs < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x07);
}
void MIPSXEmitter::SLT(MIPSReg rd, MIPSReg rs, MIPSReg rt) { void MIPSXEmitter::SLT(MIPSReg rd, MIPSReg rs, MIPSReg rt) {
// 000000 sssss ttttt ddddd 00000101010 // 000000 sssss ttttt ddddd xxxxx 101010
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && rs < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x2a); Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x2a);
} }
void MIPSXEmitter::SLTU(MIPSReg rd, MIPSReg rs, MIPSReg rt) {
// 000000 sssss ttttt ddddd xxxxx 101011
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && rs < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x2b);
}
void MIPSXEmitter::SLTI(MIPSReg rt, MIPSReg rs, s16 imm) { void MIPSXEmitter::SLTI(MIPSReg rt, MIPSReg rs, s16 imm) {
// 001010 sssss ttttt iiiiiiiiiiiiiiii // 001010 sssss ttttt iiiiiiiiiiiiiiii
_dbg_assert_msg_(JIT, rs < F_BASE && rt < F_BASE, "Bad emitter arguments"); _dbg_assert_msg_(JIT, rs < F_BASE && rt < F_BASE, "Bad emitter arguments");
@ -241,38 +273,18 @@ void MIPSXEmitter::SLTIU(MIPSReg rt, MIPSReg rs, s16 imm) {
Write32Fields(26, 0x0b, 21, rs, 16, rt, 0, (u16)imm); Write32Fields(26, 0x0b, 21, rs, 16, rt, 0, (u16)imm);
} }
void MIPSXEmitter::SRL(MIPSReg rd, MIPSReg rt, u8 sa) { void MIPSXEmitter::ADDU(MIPSReg rd, MIPSReg rs, MIPSReg rt) {
// 000000 xxxxx ttttt ddddd aaaaa 000010 // 000000 sssss ttttt ddddd 00000100001
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && sa <= 0x1f, "Bad emitter arguments"); _dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && rs < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x00, 16, rt, 11, rd, 6, sa & 0x1f, 0, 0x02); Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x21);
}
void MIPSXEmitter::SRLV(MIPSReg rd, MIPSReg rt, MIPSReg rs) {
// 000000 sssss ttttt ddddd 00000000110
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x06);
}
void MIPSXEmitter::SRA(MIPSReg rd, MIPSReg rt, u8 sa) {
// 000000 xxxxx ttttt ddddd aaaaa 000011
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && sa <= 0x1f, "Bad emitter arguments");
Write32Fields(26, 0x00, 16, rt, 11, rd, 6, sa & 0x1f, 0, 0x03);
}
void MIPSXEmitter::SUB(MIPSReg rd, MIPSReg rs, MIPSReg rt) {
// 000000 sssss ttttt ddddd 00000100010
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x22);
} }
void MIPSXEmitter::SUBU(MIPSReg rd, MIPSReg rs, MIPSReg rt) { void MIPSXEmitter::SUBU(MIPSReg rd, MIPSReg rs, MIPSReg rt) {
// 000000 sssss ttttt ddddd 00000100011 // 000000 sssss ttttt ddddd 00000100011
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && rs < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x23); Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x23);
} }
void MIPSXEmitter::ADDU(MIPSReg rd, MIPSReg rs, MIPSReg rt) {
// 000000 sssss ttttt ddddd 00000100001
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x21);
}
void MIPSXEmitter::ADDIU(MIPSReg rt, MIPSReg rs, s16 imm) { void MIPSXEmitter::ADDIU(MIPSReg rt, MIPSReg rs, s16 imm) {
// 001001 sssss ttttt iiiiiiiiiiiiiiii // 001001 sssss ttttt iiiiiiiiiiiiiiii
_dbg_assert_msg_(JIT, rs < F_BASE && rt < F_BASE, "Bad emitter arguments"); _dbg_assert_msg_(JIT, rs < F_BASE && rt < F_BASE, "Bad emitter arguments");
@ -281,36 +293,40 @@ void MIPSXEmitter::ADDIU(MIPSReg rt, MIPSReg rs, s16 imm) {
void MIPSXEmitter::AND(MIPSReg rd, MIPSReg rs, MIPSReg rt) { void MIPSXEmitter::AND(MIPSReg rd, MIPSReg rs, MIPSReg rt) {
// 000000 sssss ttttt ddddd 00000100100 // 000000 sssss ttttt ddddd 00000100100
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && rs < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x24); Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x24);
} }
void MIPSXEmitter::OR(MIPSReg rd, MIPSReg rs, MIPSReg rt) {
// 000000 sssss ttttt ddddd 00000100101
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && rs < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x25);
}
void MIPSXEmitter::XOR(MIPSReg rd, MIPSReg rs, MIPSReg rt) {
// 000000 sssss ttttt ddddd 00000100110
_dbg_assert_msg_(JIT, rd < F_BASE && rt < F_BASE && rs < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x26);
}
void MIPSXEmitter::ANDI(MIPSReg rt, MIPSReg rs, s16 imm) { void MIPSXEmitter::ANDI(MIPSReg rt, MIPSReg rs, s16 imm) {
// 001100 sssss ttttt iiiiiiiiiiiiiiii // 001100 sssss ttttt iiiiiiiiiiiiiiii
_dbg_assert_msg_(JIT, rs < F_BASE && rt < F_BASE, "Bad emitter arguments"); _dbg_assert_msg_(JIT, rs < F_BASE && rt < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x0c, 21, rs, 16, rt, 0, (u16)imm); Write32Fields(26, 0x0c, 21, rs, 16, rt, 0, (u16)imm);
} }
void MIPSXEmitter::OR(MIPSReg rd, MIPSReg rs, MIPSReg rt) {
// 000000 sssss ttttt ddddd 00000100101
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x25);
}
void MIPSXEmitter::ORI(MIPSReg rt, MIPSReg rs, s16 imm) { void MIPSXEmitter::ORI(MIPSReg rt, MIPSReg rs, s16 imm) {
// 001101 sssss ttttt iiiiiiiiiiiiiiii // 001101 sssss ttttt iiiiiiiiiiiiiiii
_dbg_assert_msg_(JIT, rs < F_BASE && rt < F_BASE, "Bad emitter arguments"); _dbg_assert_msg_(JIT, rs < F_BASE && rt < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x0d, 21, rs, 16, rt, 0, (u16)imm); Write32Fields(26, 0x0d, 21, rs, 16, rt, 0, (u16)imm);
} }
void MIPSXEmitter::XOR(MIPSReg rd, MIPSReg rs, MIPSReg rt) {
// 000000 sssss ttttt ddddd 00000100110
Write32Fields(26, 0x00, 21, rs, 16, rt, 11, rd, 0, 0x26);
}
void MIPSXEmitter::XORI(MIPSReg rt, MIPSReg rs, s16 imm) { void MIPSXEmitter::XORI(MIPSReg rt, MIPSReg rs, s16 imm) {
// 001110 sssss ttttt iiiiiiiiiiiiiiii // 001110 sssss ttttt iiiiiiiiiiiiiiii
_dbg_assert_msg_(JIT, rs < F_BASE && rt < F_BASE, "Bad emitter arguments"); _dbg_assert_msg_(JIT, rs < F_BASE && rt < F_BASE, "Bad emitter arguments");
Write32Fields(26, 0x0e, 21, rs, 16, rt, 0, (u16)imm); Write32Fields(26, 0x0e, 21, rs, 16, rt, 0, (u16)imm);
} }
void MIPSXEmitter::LUI(MIPSReg rt, s16 imm) { void MIPSXEmitter::LUI(MIPSReg rt, s16 imm) {
// 001111 sssss ttttt iiiiiiiiiiiiiiii // 001111 sssss ttttt iiiiiiiiiiiiiiii
_dbg_assert_msg_(JIT, rt < F_BASE, "Bad emitter arguments"); _dbg_assert_msg_(JIT, rt < F_BASE, "Bad emitter arguments");

26
Common/MipsEmitter.h
View File

@ -134,26 +134,32 @@ public:
void SB(MIPSReg value, MIPSReg base, s16 offset); void SB(MIPSReg value, MIPSReg base, s16 offset);
void SW(MIPSReg value, MIPSReg base, s16 offset); void SW(MIPSReg value, MIPSReg base, s16 offset);
// The imm is sign extended before those with s16 imm.
void SLL(MIPSReg rd, MIPSReg rt, u8 sa); void SLL(MIPSReg rd, MIPSReg rt, u8 sa);
void SLT(MIPSReg rd, MIPSReg rt, MIPSReg rs);
void SLTI(MIPSReg rd, MIPSReg rt, s16 imm);
void SLTIU(MIPSReg rt, MIPSReg rs, s16 imm);
void SLLV(MIPSReg rd, MIPSReg rt, MIPSReg rs);
void SRL(MIPSReg rd, MIPSReg rt, u8 sa); void SRL(MIPSReg rd, MIPSReg rt, u8 sa);
void SRLV(MIPSReg rd, MIPSReg rt, MIPSReg rs);
void SRA(MIPSReg rd, MIPSReg rt, u8 sa); void SRA(MIPSReg rd, MIPSReg rt, u8 sa);
void SLLV(MIPSReg rd, MIPSReg rt, MIPSReg rs);
void SRLV(MIPSReg rd, MIPSReg rt, MIPSReg rs);
void SRAV(MIPSReg rd, MIPSReg rt, MIPSReg rs);
void SUB(MIPSReg rd, MIPSReg rs, MIPSReg rt); void SLT(MIPSReg rd, MIPSReg rt, MIPSReg rs);
void SUBU(MIPSReg rd, MIPSReg rs, MIPSReg rt); void SLTU(MIPSReg rd, MIPSReg rt, MIPSReg rs);
void SLTI(MIPSReg rd, MIPSReg rt, s16 imm);
// Note: very importantly, *sign* extends imm before an unsigned compare.
void SLTIU(MIPSReg rt, MIPSReg rs, s16 imm);
// ADD/SUB/ADDI intentionally omitted. They are just versions that trap.
void ADDU(MIPSReg rd, MIPSReg rs, MIPSReg rt); void ADDU(MIPSReg rd, MIPSReg rs, MIPSReg rt);
void SUBU(MIPSReg rd, MIPSReg rs, MIPSReg rt);
void ADDIU(MIPSReg rt, MIPSReg rs, s16 imm); void ADDIU(MIPSReg rt, MIPSReg rs, s16 imm);
void SUBIU(MIPSReg rt, MIPSReg rs, s16 imm) {
ADDIU(rt, rs, -imm);
}
void AND(MIPSReg rd, MIPSReg rs, MIPSReg rt); void AND(MIPSReg rd, MIPSReg rs, MIPSReg rt);
void ANDI(MIPSReg rt, MIPSReg rs, s16 imm);
void OR(MIPSReg rd, MIPSReg rs, MIPSReg rt); void OR(MIPSReg rd, MIPSReg rs, MIPSReg rt);
void ORI(MIPSReg rt, MIPSReg rs, s16 imm);
void XOR(MIPSReg rd, MIPSReg rs, MIPSReg rt); void XOR(MIPSReg rd, MIPSReg rs, MIPSReg rt);
void ANDI(MIPSReg rt, MIPSReg rs, s16 imm);
void ORI(MIPSReg rt, MIPSReg rs, s16 imm);
void XORI(MIPSReg rt, MIPSReg rs, s16 imm); void XORI(MIPSReg rt, MIPSReg rs, s16 imm);
// Clears the lower bits. // Clears the lower bits.